公开(公告)号：US20200294610A1

公开(公告)日：2020-09-17

申请号：US16562482

申请日：2019-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Marie TAKADA ,  Masanobu SHIRAKAWA ,  Yoshihiro UEDA ,  Naomi TAKEDA ,  Hideki YAMADA

IPC: G11C19/08 ,  G11C11/16 ,  G06F3/06

Abstract: According to one embodiment, a magnetic memory puts a first magnetic domain having a magnetization direction which is the same as or opposite to a magnetic domain of a first layer of a magnetic memory line, into the first layer, based on a value of data and the magnetization direction of the first layer. When receiving a first command, the magnetic memory puts a first additional magnetic domain and a second additional magnetic domain having a magnetization direction opposite to the first additional magnetic domain into the magnetic memory line. When receiving a second command, the magnetic memory read the first and second additional magnetic domains to determine the magnetization direction of the first magnetic domain.

公开(公告)号：US20200005059A1

公开(公告)日：2020-01-02

申请号：US16567863

申请日：2019-09-11

Applicant: Toshiba Memory Corporation

Inventor： Hideki YAMADA ,  Masanobu SHIRAKAWA ,  Marie KURONAGA

IPC: G06K9/00 ,  G01C21/34 ,  G05D1/00 ,  G01C21/36 ,  H04W4/40

Abstract: According to one embodiment, an information processing device includes: a first memory; a first receiver; a first determination section; and a first transmitter. The first memory is configured to store first image data of interior of a vehicle at a first point in time. The first receiver is configured to receive second image data of the interior of the vehicle at a second point of time from the vehicle. The first determination section is configured to determine whether a change has been caused in the interior of the vehicle between the first point in time and the second point in time. The first transmitter is configured to transmit first data based on the determination result.

公开(公告)号：US20190295634A1

公开(公告)日：2019-09-26

申请号：US16120827

申请日：2018-09-04

Applicant: Toshiba Memory Corporation

Inventor： Kuminori HYODO ,  Kenji SAKURADA ,  Masanobu SHIRAKAWA ,  Hideki YAMADA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G06F12/02

Abstract: A memory system according to an embodiment includes a semiconductor memory and a memory controller. The semiconductor memory includes memory cells and a sequencer. Each of the memory cells stores first data when it has a first threshold voltage, and stores second data when it has a second threshold voltage. The sequencer performs a first write operation for write data. In the first write operation, the sequencer executes a program loop repeatedly and terminates the first write operation, when the verify operation for the first data has passed and the verify operation for the second data has not passed. The sequencer performs a second write operation for the write data based on a first command from the memory controller after the first write operation is terminated.

公开(公告)号：US20210183455A1

公开(公告)日：2021-06-17

申请号：US17190125

申请日：2021-03-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hideki YAMADA ,  Masanobu SHIRAKAWA

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/32

Abstract: A memory system includes a semiconductor storage device including a memory cell array including a plurality of groups of memory cells, and a control circuit configured to perform, upon receipt of a write command, a write operation on one of the groups of memory cells, and a memory controller is configured to, when transmitting the write command to perform the write operation on the one of the groups of memory cells, determine a first write voltage value for the write operation based on a total number of write operations or erase operations that have been performed on the one of the groups of memory cells, and transmit the write command to the semiconductor storage device together with the determined first write voltage value.

公开(公告)号：US20200234776A1

公开(公告)日：2020-07-23

申请号：US16548136

申请日：2019-08-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hideki YAMADA ,  Masanobu SHIRAKAWA

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/32

Abstract: A memory system includes a semiconductor storage device including a memory cell array including a plurality of groups of memory cells, and a control circuit configured to perform, upon receipt of a write command, a write operation on one of the groups of memory cells, and a memory controller is configured to, when transmitting the write command to perform the write operation on the one of the groups of memory cells, determine a first write voltage value for the write operation based on a total number of write operations or erase operations that have been performed on the one of the groups of memory cells, and transmit the write command to the semiconductor storage device together with the determined first write voltage value.