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公开(公告)号：US20220108754A1
公开(公告)日：2022-04-07
申请号：US17554710
申请日：2021-12-17
发明人： Masanobu SHIRAKAWA
IPC分类号： G11C16/26 , G11C11/56 , H01L27/1157 , G11C7/06 , G11C16/34 , H01L27/11582 , G11C16/10
摘要： According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.
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公开(公告)号：US20210295909A1
公开(公告)日：2021-09-23
申请号：US17343426
申请日：2021-06-09
摘要： According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.
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公开(公告)号：US20210193228A1
公开(公告)日：2021-06-24
申请号：US17196140
申请日：2021-03-09
发明人： Masanobu SHIRAKAWA , Kenta YASUFUKU , Akira YAMAGA
摘要： A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.
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公开(公告)号：US20210183455A1
公开(公告)日：2021-06-17
申请号：US17190125
申请日：2021-03-02
发明人： Hideki YAMADA , Masanobu SHIRAKAWA
摘要： A memory system includes a semiconductor storage device including a memory cell array including a plurality of groups of memory cells, and a control circuit configured to perform, upon receipt of a write command, a write operation on one of the groups of memory cells, and a memory controller is configured to, when transmitting the write command to perform the write operation on the one of the groups of memory cells, determine a first write voltage value for the write operation based on a total number of write operations or erase operations that have been performed on the one of the groups of memory cells, and transmit the write command to the semiconductor storage device together with the determined first write voltage value.
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公开(公告)号：US20210110874A1
公开(公告)日：2021-04-15
申请号：US17131026
申请日：2020-12-22
摘要： According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.
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公开(公告)号：US20200303000A1
公开(公告)日：2020-09-24
申请号：US16564279
申请日：2019-09-09
摘要： According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.
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公开(公告)号：US20200090779A1
公开(公告)日：2020-03-19
申请号：US16294185
申请日：2019-03-06
摘要： A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.
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公开(公告)号：US20190130968A1
公开(公告)日：2019-05-02
申请号：US16219410
申请日：2018-12-13
CPC分类号： G11C11/5642 , G06F11/1068 , G11C11/5671 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/30 , G11C2211/563 , G11C2211/5642 , H01L27/1157 , H01L27/11582
摘要： According to an embodiment, a control circuitry performing: a first operation of reading data out of a memory cell with a first voltage applied to a word line while changing the first voltage by a first shift amount within a first range, and a second operation of reading data out of the memory cell with a second voltage applied to the word line while changing the second voltage by a second shift amount within a second range, wherein the second shift amount is smaller than the first shift amount, and wherein the control circuitry performs the second operation to apply the second voltage to the word line subsequently to application of the first voltage to the word line in the first operation.
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公开(公告)号：US20180204619A1
公开(公告)日：2018-07-19
申请号：US15919480
申请日：2018-03-13
CPC分类号： G11C16/0483 , G11C7/062 , G11C7/1042 , G11C8/08 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3427
摘要： A semiconductor memory device according to an embodiment includes: first to 32nd memory cells; first to 16th bit lines connected to the first to 16th memory cells; 17th to 32nd bit lines connected to the 17th to 32nd memory cells; a first word line connected to gates of the first to 32nd memory cells; first to 16th sense amplifiers configured to determine data read from the first to 16th memory cells at a first timing; and 17th to 32nd sense amplifiers configured to determine data read from the 17th to 32nd memory cells at a second timing. The first timing is different from the second timing.
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公开(公告)号：US20180075902A1
公开(公告)日：2018-03-15
申请号：US15459542
申请日：2017-03-15
CPC分类号： G11C11/5642 , G06F11/1048 , G06F11/1068 , G06F11/1072 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C29/52 , G11C2029/0411 , G11C2211/5642 , G11C2211/5643 , H03M13/2906
摘要： According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.
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