公开(公告)号：US20210151465A1

公开(公告)日：2021-05-20

申请号：US17160563

申请日：2021-01-28

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Jun IIJIMA ,  Ryota KATSUMATA ,  Kazuyuki HIGASHI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/1157 ,  H01L25/065 ,  H01L23/00

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US20190326322A1

公开(公告)日：2019-10-24

申请号：US16460410

申请日：2019-07-02

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Jun IIJIMA ,  Ryota KATSUMATA ,  Kazuyuki HIGASHI

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/00 ,  H01L23/522

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US20200176434A1

公开(公告)日：2020-06-04

申请号：US16783830

申请日：2020-02-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Jun IIJIMA ,  Yumi NAKAJIMA

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.

公开(公告)号：US20190312012A1

公开(公告)日：2019-10-10

申请号：US16390639

申请日：2019-04-22

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Ryota KATSUMATA ,  Jun IIJIMA ,  Tetsuya SHIMIZU ,  Takamasa USUI ,  Genki FUJITA

IPC: H01L25/065 ,  H01L25/00 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L23/00

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US20190088676A1

公开(公告)日：2019-03-21

申请号：US15911369

申请日：2018-03-05

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Jun IIJIMA ,  Ryota KATSUMATA ,  Kazuyuki HIGASHI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522

CPC classification number: H01L27/11582 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/26 ,  H01L23/5226 ,  H01L24/04 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US20200350291A1

公开(公告)日：2020-11-05

申请号：US16916979

申请日：2020-06-30

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Ryota KATSUMATA ,  Jun IIJIMA ,  Tetsuya SHIMIZU ,  Takamasa USUI ,  Genki FUJITA

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US20190296035A1

公开(公告)日：2019-09-26

申请号：US16127962

申请日：2018-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Jun IIJIMA ,  Masayoshi Tagami ,  Takamasa Usui ,  Takahito Nishimura

IPC: H01L27/11578 ,  H01L27/11568 ,  G11C11/24

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.

公开(公告)号：US20190287955A1

公开(公告)日：2019-09-19

申请号：US16126018

申请日：2018-09-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Jun IIJIMA ,  Yumi NAKAJIMA

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.