公开(公告)号：US20180261575A1

公开(公告)日：2018-09-13

申请号：US15706017

申请日：2017-09-15

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/08 ,  H01L25/50 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/08146 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US09887262B2

公开(公告)日：2018-02-06

申请号：US14837295

申请日：2015-08-27

Applicant: Toshiba Memory Corporation

Inventor： Yoshihiro Minami ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Masayoshi Tagami

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/06 ,  H01L23/532 ,  H01L29/788 ,  H01L29/66 ,  H01L23/522 ,  H01L27/11521

CPC classification number: H01L29/0649 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/11521 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/788

Abstract: A semiconductor device includes a semiconductor layer and a first insulating film provided on the semiconductor layer. The first insulating film has a surface opposite to the semiconductor layer, the surface including a first portion, a second portion and a third portion between the first portion and the second portion. The device includes a first interconnection provided on a first portion and a second interconnection provided on the second portion. The first interconnection and the second interconnection extend in a first direction. The device further includes a conductor and a nitride layer. The conductor extends through the first insulating film in a second direction from each of the first interconnection and the second interconnection toward the semiconductor layer, and the conductor electrically connects the first interconnection to the semiconductor layer. The nitrided layer is provided at least on the third surface.

公开(公告)号：US10741527B2

公开(公告)日：2020-08-11

申请号：US16390639

申请日：2019-04-22

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

IPC: H01L29/788 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US20190296035A1

公开(公告)日：2019-09-26

申请号：US16127962

申请日：2018-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Jun IIJIMA ,  Masayoshi Tagami ,  Takamasa Usui ,  Takahito Nishimura

IPC: H01L27/11578 ,  H01L27/11568 ,  G11C11/24

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.

公开(公告)号：US10297578B2

公开(公告)日：2019-05-21

申请号：US15706017

申请日：2017-09-15

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

IPC: H01L29/788 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.