公开(公告)号：US20200303402A1

公开(公告)日：2020-09-24

申请号：US16530221

申请日：2019-08-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shigeki KOBAYASHI ,  Taro SHIOKAWA ,  Masahisa SONODA

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.

公开(公告)号：US20190006275A1

公开(公告)日：2019-01-03

申请号：US15862665

申请日：2018-01-05

Applicant: Toshiba Memory Corporation

Inventor： Shigeki KOBAYASHI ,  Masaru Kito

IPC: H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/768

Abstract: According to one embodiment, a stacked body includes a plurality of conductive layers stacked with an insulator interposed. The stacked body includes a first stacked portion and a second stacked portion. The second stacked portion includes a plurality of terrace portions arranged in a staircase configuration with level differences in a first direction and a second direction. The second stacked portion includes a conductive portion and a spacer portion. The conductive portion is connected to the conductive layer and is provided in same layer as the conductive layer. The spacer portion is provided in same layer as the conductive layer and the conductive portion. The spacer portion is of a material different from the conductive portion.

公开(公告)号：US20190172836A1

公开(公告)日：2019-06-06

申请号：US16109370

申请日：2018-08-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shigeki KOBAYASHI ,  Hiroshi NAKAKI

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L21/768

Abstract: A storage device includes a conductive layer, a plurality of electrode layers stacked on the conductive layer, a wiring above the plurality of electrode layers, an interlayer insulating film between the plurality of electrode layers and the wiring, a semiconductor film penetrating the plurality of electrode layers and the interlayer insulating film in a stacking direction of the plurality of electrode layers, a contact plug penetrating the interlayer insulating film in the stacking direction, and connected to each of the plurality of electrode layers, and a conductive film in the vicinity of the contact plug and penetrating at least one of the plurality of electrode layers in the stacking direction. The semiconductor film is electrically connected to the conductive layer and the wiring, and an entire upper end of the conductive film is covered by an insulating layer.

公开(公告)号：US20200075625A1

公开(公告)日：2020-03-05

申请号：US16293954

申请日：2019-03-06

Applicant: Toshiba Memory Corporation

Inventor： Shigeki KOBAYASHI ,  Masaru KITO ,  Yasuhiro UCHIYAMA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/10 ,  H01L27/11573 ,  H01L23/528

Abstract: A semiconductor memory device includes: a first conductive layer and a first insulating layer extending in a first direction, these layers being arranged in a second direction intersecting the first direction; a first semiconductor layer opposed to the first conductive layer, and extending in a third direction intersecting the first and second directions; a second semiconductor layer opposed to the first conductive layer, extending in the third direction; a first contact electrode connected to the first semiconductor layer; and a second contact electrode connected to the second semiconductor layer. In a first cross section extending in the first and second directions, an entire outer peripheral surface of the first semiconductor layer is surrounded by the first conductive layer, and an outer peripheral surface of the second semiconductor layer is surrounded by the first conductive layer and the first insulating layer.

公开(公告)号：US20190296040A1

公开(公告)日：2019-09-26

申请号：US16122258

申请日：2018-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kotaro FUJII ,  Masahisa SONODA ,  Masaru KITO ,  Satoshi NAGASHIMA ,  Shigeki KOBAYASHI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/14 ,  G11C16/08

Abstract: A semiconductor device according to an embodiment includes first conductors, first pillars, a pillar column. Each of the first pillars is provided through the first conductors. The pillar column includes second pillars that are aligned in a first direction. Each of the second pillars is provided through the first conductors. The pillar column includes first and second columns of the second pillars. The first and second columns of the second pillars are aligned in a second direction that intersects the first direction. The first pillars are arranged on both sides in the second direction of each pillar column. The first conductors are provided continuously on both sides in the second direction of the second pillars that are included in each pillar column.

公开(公告)号：US20180261614A1

公开(公告)日：2018-09-13

申请号：US15700393

申请日：2017-09-11

Applicant: Toshiba Memory Corporation

Inventor： Shigeki KOBAYASHI ,  Takamasa OKAWA

IPC: H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory device includes an interconnect layer including a conductive layer and a semiconductor layer of a first conductivity type provided on the conductive layer; a stacked body including a plurality of electrode layers stacked on the interconnect layer, a semiconductor pillar provided in the stacked body and extending through the plurality of electrode layers in a stacking direction thereof; and an insulating layer provided on the interconnect layer and extending along a lateral surface of the stacked body. The semiconductor layer includes a first semiconductor region of a second conductivity type positioned between the insulating layer and the conductive layer, and the first semiconductor region is in contact with the conductive layer.