公开(公告)号：US20200303007A1

公开(公告)日：2020-09-24

申请号：US16566694

申请日：2019-09-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yutaka SHIRAI

IPC: G11C13/00 ,  H01L45/00

Abstract: According to one embodiment, a device includes: a memory cell between the first and second interconnects; a first circuit in a domain having a range of a first voltage to a second voltage higher than the first voltage, the first circuit controlling supply of the second voltage to the first interconnect; a second circuit in a domain having a range of a third voltage lower than the first voltage to the first voltage, the second circuit controlling supply of the third voltage to the second interconnect; and a third circuit in a domain having a range of a fourth voltage lower than the first voltage to a fifth voltage higher than the first voltage, the third circuit controlling supply of a sixth voltage to the first and second interconnects.

公开(公告)号：US20180075892A1

公开(公告)日：2018-03-15

申请号：US15455906

申请日：2017-03-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keisuke NAKATSUKA ,  Tsuneo INABA ,  Yutaka SHIRAI

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/04 ,  G11C7/065 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/28

Abstract: According to one embodiment, a semiconductor memory device comprises: first to fourth memory cells, each of which is configured to have a first resistance state or a second resistance state; and a first circuit configured to output first data based on a first signal representing a resistance state of the first memory cell and a second signal representing a resistance state of the second memory cell, output second data based on the second signal and a third signal representing a resistance state of the third memory cell, and output third data based on the third signal and a fourth signal representing a resistance state of the fourth memory cell.