公开(公告)号：US11261539B2

公开(公告)日：2022-03-01

申请号：US16495282

申请日：2018-03-20

Applicant: Toyo Tanso Co., Ltd.

Inventor： Satoshi Torimi ,  Yusuke Sudo ,  Masato Shinohara ,  Youji Teramoto ,  Takuya Sakaguchi ,  Satoru Nogami ,  Makoto Kitabatake

IPC: H01L21/02 ,  C30B25/18 ,  C30B29/36 ,  H01L29/34 ,  H01L29/16 ,  C30B25/20

Abstract: In a method for manufacturing a reformed SiC wafer 41 (a surface treatment method for a SiC wafer) having its surface that is reformed by processing an untreated SiC wafer 40 before formation of an epitaxial layer 42, the method includes a surface reforming step as described below. That is, the untreated SiC wafer 40 includes BPDs as dislocations parallel to an inside of a (0001) face, and TEDs. Property of the surface of the untreated SiC wafer 40 is changed so as to have higher rate in which portions having BPDs on the surface of the untreated SiC wafer 40 propagate as TEDs at a time of forming the epitaxial layer 42.

公开(公告)号：US20220376109A1

公开(公告)日：2022-11-24

申请号：US17642811

申请日：2020-06-18

Applicant: Hitachi, Ltd. ,  TOYO TANSO CO., LTD

Inventor： Keisuke Kobayashi ,  Kumiko Konishi ,  Akio Shima ,  Norihito Yabuki ,  Yusuke Sudoh ,  Satoru Nogami ,  Makoto Kitabatake

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L21/04

Abstract: To provide a technique capable of improving performance and reliability of a semiconductor device. An n−-type epitaxial layer (12) is formed on an n-type semiconductor substrate (11), and a p+-type body region (14), n+-type current spreading regions (16, 17), and a trench. TR are formed in the n−-type epitaxial layer (12). A bottom surface B1 of the trench TR is located in the p+-type body region (14), a side surface S1 of the trench TR is in contact with the n+-type current spreading region (17), and a side surface S2 of the trench TR is in contact with the n+-type current spreading region (16). Here, a ratio of silicon is higher than a ratio of carbon in an upper surface T1 of the n−-type epitaxial layer (12), and the bottom surface B1, the side surface S1, and the side surface 32 of the trench. Furthermore, an angle θ1 at which the upper surface T1 of the n−-type epitaxial layer (12) is inclined with respect to the side surface S1 is smaller than an angle θ2 at which the upper surface T1 of the n−-type epitaxial layer (12) is inclined with respect to the side surface S2.

公开(公告)号：US20200095703A1

公开(公告)日：2020-03-26

申请号：US16495282

申请日：2018-03-20

Applicant: Toyo Tanso Co., Ltd.

Inventor： Satoshi Torimi ,  Yusuke Sudo ,  Masato Shinohara ,  Youji Teramoto ,  Takuya Sakaguchi ,  Satoru Nogami ,  Makoto Kitabatake

IPC: C30B25/18 ,  H01L21/02 ,  H01L29/34 ,  H01L29/16 ,  C30B25/20 ,  C30B29/36

Abstract: In a method for manufacturing a reformed SiC wafer 41 (a surface treatment method for a SiC wafer) having its surface that is reformed by processing an untreated SiC wafer 40 before formation of an epitaxial layer 42, the method includes a surface reforming step as described below. That is, the untreated SiC wafer 40 includes BPDs as dislocations parallel to an inside of a (0001) face, and TEDs. Property of the surface of the untreated SiC wafer 40 is changed so as to have higher rate in which portions having BPDs on the surface of the untreated SiC wafer 40 propagate as TEDs at a time of forming the epitaxial layer 42.

公开(公告)号：US20170236905A1

公开(公告)日：2017-08-17

申请号：US15360498

申请日：2016-11-23

Applicant: TOYO TANSO CO., LTD.

Inventor： Satoshi Torimi ,  Masato Shinohara ,  Youji Teramoto ,  Norihito Yabuki ,  Satoru Nogami ,  Makoto Kitabatake

IPC: H01L29/16 ,  H01L21/02 ,  H01L21/304 ,  H01L21/306 ,  H01L21/04 ,  H01L23/544

CPC classification number: H01L29/1608 ,  H01L21/02008 ,  H01L21/02016 ,  H01L21/02019 ,  H01L21/0475 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/3065 ,  H01L23/544 ,  H01L2223/54433

Abstract: Provided is a method for manufacturing a thin SiC wafer by which a SiC wafer is thinned using a method without generating crack or the like, the method in which polishing after adjusting the thickness of the SiC wafer can be omitted. The method for manufacturing the thin SiC wafer 40 includes a thinning step. In the thinning step, the thickness of the SiC wafer 40 can be decreased to 100 μm or less by performing the Si vapor pressure etching in which the surface of the SiC wafer 40 is etched by heating the SiC wafer 40 after cutting out of an ingot 4 under Si vapor pressure.