公开(公告)号：US20160118124A1

公开(公告)日：2016-04-28

申请号：US14877557

申请日：2015-10-07

申请人： Tadao Nakamura ,  Michael J. Flynn

发明人： Tadao Nakamura ,  Michael J. Flynn

IPC分类号： G11C16/10 ,  G11C16/32

CPC分类号： G11C16/10 ,  G11C16/32 ,  G11C19/184 ,  G11C19/28 ,  G11C19/282

摘要： A direct-transfer marching memory includes an array of memory units, each of the memory units having a sequence of bit-level cells so as to store information of byte size or word size, the information of byte size or word size is transferred synchronously, step by step, along a direction orthogonal to a direction of the sequence of bit-level cells, each of the bit-level cells encompassing an electron-storage region configured to accumulate cell-electrons. The cell-electrons accumulated in an electron-storage region in a subject memory unit is directly transferred to an adjacent electron-storage region, which is assigned in the next memory unit adjacent to the subject memory unit, the transfer of the cell-electrons is directly controlled by control signals, without using a combinational function of a logic gate circuit.

摘要翻译： 直接传送行进存储器包括存储器单元阵列，每个存储器单元具有位级单元的序列，以便存储字节大小或字大小的信息，字节大小或字大小的信息被同步传送， 沿着与位电平单元序列的方向正交的方向，每个位层单元包含构成为积累电池电子的电子存储区域。 积存在被摄体存储单元的电子存储区域中的电池 - 电子被直接转移到与被摄体存储单元相邻的下一个存储单元中分配的相邻的电子存储区域，电池 - 电子的转移 由控制信号直接控制，不使用逻辑门电路的组合功能。

公开(公告)号：US11164612B2

公开(公告)日：2021-11-02

申请号：US16744849

申请日：2020-01-16

申请人： Tadao Nakamura ,  Michael J. Flynn

发明人： Tadao Nakamura ,  Michael J. Flynn

IPC分类号： G11C7/22 ,  G11C19/28 ,  G11C19/18

摘要： A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

公开(公告)号：US10573359B2

公开(公告)日：2020-02-25

申请号：US14450705

申请日：2014-08-04

申请人： Tadao Nakamura ,  Michael J. Flynn

发明人： Tadao Nakamura ,  Michael J. Flynn

IPC分类号： G11C7/22 ,  G11C19/28 ,  G11C19/18

摘要： A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

公开(公告)号：US09449696B2

公开(公告)日：2016-09-20

申请号：US14877557

申请日：2015-10-07

申请人： Tadao Nakamura ,  Michael J. Flynn

发明人： Tadao Nakamura ,  Michael J. Flynn

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C19/28 ,  G11C19/18 ,  G11C16/32

CPC分类号： G11C16/10 ,  G11C16/32 ,  G11C19/184 ,  G11C19/28 ,  G11C19/282

摘要： A direct-transfer marching memory includes an array of memory units, each of the memory units having a sequence of bit-level cells so as to store information of byte size or word size, the information of byte size or word size is transferred synchronously, step by step, along a direction orthogonal to a direction of the sequence of bit-level cells, each of the bit-level cells encompassing an electron-storage region configured to accumulate cell-electrons. The cell-electrons accumulated in an electron-storage region in a subject memory unit is directly transferred to an adjacent electron-storage region, which is assigned in the next memory unit adjacent to the subject memory unit, the transfer of the cell-electrons is directly controlled by control signals, without using a combinational function of a logic gate circuit.

摘要翻译： 直接传送行进存储器包括存储器单元阵列，每个存储器单元具有位级单元的序列，以便存储字节大小或字大小的信息，字节大小或字大小的信息被同步传送， 沿着与位电平单元序列的方向正交的方向，每个位层单元包含构成为积累电池电子的电子存储区域。 积存在被摄体存储单元的电子存储区域中的电池 - 电子被直接转移到与被摄体存储单元相邻的下一个存储单元中分配的相邻的电子存储区域，电池 - 电子的转移 由控制信号直接控制，不使用逻辑门电路的组合功能。

公开(公告)号：US08949650B2

公开(公告)日：2015-02-03

申请号：US13384774

申请日：2010-07-20

申请人： Tadao Nakamura ,  Michael J. Flynn

发明人： Tadao Nakamura ,  Michael J. Flynn

IPC分类号： G06F1/12 ,  G06F1/08 ,  G06F15/78 ,  G06F5/06 ,  G06F5/08 ,  G06F9/30 ,  G06F9/38 ,  G11C19/18

CPC分类号： G11C7/1072 ,  G06F1/08 ,  G06F5/065 ,  G06F5/08 ,  G06F7/57 ,  G06F9/30134 ,  G06F9/3889 ,  G06F12/0875 ,  G06F15/7821 ,  G11C19/184 ,  Y02D10/12 ,  Y02D10/13

摘要： A computer system encompasses a processor (11) including a control unit (111) and an ALU (112) configured to execute arithmetic and logic operations synchronized with the clock signal, and a marching main memory (31), which embraces an array of memory units, configured to store information in each of memory units and to transfer synchronously with the clock signal, providing the processor (11) with the stored information actively and sequentially so that the ALU (112) can execute the arithmetic and logic operations with the stored information. The results of the processing in the ALU (112) are sent out to the marching main memory (31), but there is only one way of instructions flow from the marching main memory (31) to the processor.

摘要翻译： 计算机系统包括包括控制单元（111）和被配置为执行与时钟信号同步的算术和逻辑运算的ALU（112）的处理器（11）和包含存储器阵列的行进主存储器（31） 单元，被配置为在每个存储器单元中存储信息并且与时钟信号同步地传送，主动且顺序地向处理器（11）提供所存储的信息，使得ALU（112）可以使用所存储的数据执行算术和逻辑运算 信息。 ALU（112）中的处理结果被发送到行进主存储器（31），但是只有一种指令从行进主存储器（31）流向处理器。

公开(公告)号：US20120117412A1

公开(公告)日：2012-05-10

申请号：US13384774

申请日：2010-07-20

申请人： Tadao Nakamura ,  Michael J. Flynn

发明人： Tadao Nakamura ,  Michael J. Flynn

IPC分类号： G06F1/12

CPC分类号： G11C7/1072 ,  G06F1/08 ,  G06F5/065 ,  G06F5/08 ,  G06F7/57 ,  G06F9/30134 ,  G06F9/3889 ,  G06F12/0875 ,  G06F15/7821 ,  G11C19/184 ,  Y02D10/12 ,  Y02D10/13

摘要： A computer system encompasses a processor (11) including a control unit (111) and an ALU (112) configured to execute arithmetic and logic operations synchronized with the clock signal, and a marching main memory (31), which embraces an array of memory units, configured to store information in each of memory units and to transfer synchronously with the clock signal, providing the processor (11) with the stored information actively and sequentially so that the ALU (112) can execute the arithmetic and logic operations with the stored information. The results of the processing in the ALU (112) are sent out to the marching main memory (31), but there is only one way of instructions flow from the marching main memory (31) to the processor.

摘要翻译： 计算机系统包括包括控制单元（111）和被配置为执行与时钟信号同步的算术和逻辑运算的ALU（112）的处理器（11），以及包含存储器阵列的行进主存储器（31） 单元，被配置为在每个存储器单元中存储信息并且与时钟信号同步地传送，主动且顺序地向处理器（11）提供所存储的信息，使得ALU（112）可以使用所存储的数据执行算术和逻辑运算 信息。 ALU（112）中的处理结果被发送到行进主存储器（31），但是只有一种指令从行进主存储器（31）流向处理器。

公开(公告)号：US20200152247A1

公开(公告)日：2020-05-14

申请号：US16744849

申请日：2020-01-16

申请人： Tadao Nakamura ,  Michael J. Flynn

发明人： Tadao Nakamura ,  Michael J. Flynn

IPC分类号： G11C7/22 ,  G11C19/28 ,  G11C19/18

摘要： A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

公开(公告)号：US09361957B2

公开(公告)日：2016-06-07

申请号：US14552572

申请日：2014-11-25

申请人： Tadao Nakamura ,  Michael J. Flynn

发明人： Tadao Nakamura ,  Michael J. Flynn

IPC分类号： G06F1/12 ,  G06F1/08 ,  G11C7/10 ,  G06F15/78 ,  G06F5/08 ,  G06F9/30 ,  G06F9/38 ,  G11C19/18 ,  G06F5/06 ,  G06F12/08 ,  G06F7/57

CPC分类号： G11C7/1072 ,  G06F1/08 ,  G06F5/065 ,  G06F5/08 ,  G06F7/57 ,  G06F9/30134 ,  G06F9/3889 ,  G06F12/0875 ,  G06F15/7821 ,  G11C19/184 ,  Y02D10/12 ,  Y02D10/13

摘要： A computer system encompasses a processor (11) including a control unit (111) and an ALU (112) configured to execute arithmetic and logic operations synchronized with the clock signal, and a marching main memory (31), which embraces an array of memory units, configured to store information in each of memory units and to transfer synchronously with the clock signal, providing the processor (11) with the stored information actively and sequentially so that the ALU (112) can execute the arithmetic and logic operations with the stored information. The results of the processing in the ALU (112) are sent out to the marching main memory (31), but there is only one way of instructions flow from the marching main memory (31) to the processor.

摘要翻译： 计算机系统包括包括控制单元（111）和被配置为执行与时钟信号同步的算术和逻辑运算的ALU（112）的处理器（11）和包含存储器阵列的行进主存储器（31） 单元，被配置为在每个存储器单元中存储信息并且与时钟信号同步地传送，主动且顺序地向处理器（11）提供所存储的信息，使得ALU（112）可以使用所存储的数据执行算术和逻辑运算 信息。 ALU（112）中的处理结果被发送到行进主存储器（31），但是只有一种指令从行进主存储器（31）流向处理器。

公开(公告)号：US20140344544A1

公开(公告)日：2014-11-20

申请号：US14450705

申请日：2014-08-04

申请人： Tado Nakamura ,  Michael J. Flynn

发明人： Tadao Nakamura ,  Michael J. Flynn

IPC分类号： G11C7/22

CPC分类号： G11C7/22 ,  G11C19/184 ,  G11C19/186 ,  G11C19/188 ,  G11C19/28 ,  G11C19/287

摘要： A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

摘要翻译： 公开了一种具有存储器单元阵列的行进存储器。 每个存储器单元具有位级单元的序列。 每个位电平单元具有转移晶体管，其具有通过第一延迟元件连接到时钟信号供给线的第一主电极和连接到位于第一延迟元件的第一相邻位电平的输出端的控制电极 通过第二延迟元件的存储器单元的阵列的输入侧。 每个位电平单元还具有复位晶体管，其具有连接到转移晶体管的第二主电极的第一主电极，连接到时钟信号供给线的控制电极和连接到 地面潜力。 每个位电平单元还具有与复位晶体管并联连接的电容器。

公开(公告)号：US08625069B2

公开(公告)日：2014-01-07

申请号：US12141216

申请日：2008-06-18

申请人： Nobuhiko Yabu ,  Tadao Nakamura

发明人： Nobuhiko Yabu ,  Tadao Nakamura

IPC分类号： G03B27/68 ,  G03B27/52

CPC分类号： G03B27/42 ,  G03F7/70258 ,  G03F7/70358

摘要： An exposure apparatus the present invention comprises: an illumination optical system configured to illuminate an illumination area on an original with light from a light source; a projection optical system configured to project a pattern of the original onto a substrate; a first stage configured to hold the original; a second stage configured to hold the substrate; and a controller configured to control driving of at least one of the first stage, the second stage, and an optical element which forms the projection optical system so as to reduce variations in imaging characteristics of the projection optical system, based on a dependence of a transmittance of the pattern on a position in the illumination area.

摘要翻译： 本发明的曝光装置包括：照明光学系统，被配置为用来自光源的光照射原稿上的照明区域; 投影光学系统，被配置为将原稿的图案投影到基板上; 第一阶段配置为保持原件; 第二级，被配置为保持所述衬底; 以及控制器，其被配置为基于所述投影光学系统的依赖性来控制形成所述投影光学系统的所述第一级，所述第二级和光学元件中的至少一个的驱动，以便减少所述投影光学系统的成像特性的变化 图案在照明区域中的位置的透射率。