公开(公告)号：US5210048A

公开(公告)日：1993-05-11

申请号：US924521

申请日：1992-08-04

申请人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

发明人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0425

摘要： Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate. A floating gate transistor is constituted to include the substrate, source and drain regions, second insulation film, floating gate, third insulation film and control gate. An offset transistor is constituted to include the substrate, source and drain regions, third insulation film and control gate. The first insulation film and the impurity region are used as an element isolation region of a memory cell.

摘要翻译： 在第一导电类型的半导体衬底的表面区域中形成第二导电类型的源区和漏区。 在基板的源极和漏极区域上形成第一绝缘膜。 在位于源区和漏区之间的衬底的该部分上形成具有隧道效应的第二薄绝缘膜。 在第二绝缘膜上形成浮栅。 在第一绝缘膜，浮栅和位于源极和漏极区之间的基板的那部分上形成第三绝缘膜，并且在其上不形成第二绝缘膜。 在第三绝缘膜上以与源极和漏极区相交的方向延伸的条形形成控制栅极。 在除了源极和漏极区域以及位于控制栅极下方的部分之外，在衬底中形成具有比衬底高的杂质浓度的第一导电类型的杂质区域。 浮栅晶体管构成为包括基板，源极和漏极区，第二绝缘膜，浮栅，第三绝缘膜和控制栅。 偏移晶体管构成为包括基板，源极和漏极区域，第三绝缘膜和控制栅极。 第一绝缘膜和杂质区用作存储单元的元件隔离区。

公开(公告)号：US5053841A

公开(公告)日：1991-10-01

申请号：US423362

申请日：1989-10-18

申请人： Tadashi Miyakawa ,  Masamichi Asano ,  Tadayuki Taura ,  Atsushi Shoji ,  Michiharu Inami

发明人： Tadashi Miyakawa ,  Masamichi Asano ,  Tadayuki Taura ,  Atsushi Shoji ,  Michiharu Inami

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7886

摘要： A nonvolatile semiconductor memory includes a cell array in which electrically erasable programmable nonvolatile semiconductor memory cells, each using a cell transistor having source and drain regions in a semiconductor substrate, and a gate electrode with a three-layered structure on the semiconductor substrate are arranged in a matrix form. In the gate electrode having the three-layered structure, a first-layer floating gate electrode opposes a semiconductor substrate surface through a first gate insulating film, and a second- or third-layer gate electrode serves as one of erase and control gate electrodes. The erase gate electrode opposes a part of the floating gate electrode through a tunnel insulating film, and the control gate electrode opposes the floating gate electrode through a second gate insulating film. The erase and control gate electrodes are arranged to be parallel to each other, and to be perpendicular to the source and drain regions. Of two cell transistors adjacent to each other in a length direction of the channel region, the source region of one cell transistor is common to the drain region of the other cell transistor, and the cell transistors adjacent to each other in the widthwise direction of the channel region are element-isolated by an element isolation region formed in the semiconductor substrate between the channel regions.

摘要翻译： 非易失性半导体存储器包括：单元阵列，其中在半导体衬底中使用具有源极和漏极区域的单元晶体管和半导体衬底上具有三层结构的栅电极的电可擦除可编程非易失性半导体存储器单元布置在 矩阵形式。 在具有三层结构的栅电极中，第一层浮置栅电极通过第一栅极绝缘膜与半导体衬底表面相对，并且第二或第三层栅极用作擦除和控制栅电极之一。 擦除栅电极通过隧道绝缘膜与浮栅的一部分相对，并且控制栅电极通过第二栅极绝缘膜与浮栅电极相对。 擦除和控制栅电极被布置成彼此平行并且垂直于源区和漏区。 在沟道区域的长度方向上彼此相邻的两个单元晶体管中，一个单元晶体管的源极区域与另一个单元晶体管的漏极区域相同，并且在晶体管的宽度方向上彼此相邻的单元晶体管 沟道区域通过形成在沟道区域之间的半导体衬底中的元件隔离区元件隔离。

公开(公告)号：US5153684A

公开(公告)日：1992-10-06

申请号：US734109

申请日：1991-07-24

申请人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

发明人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： G11C16/0425 ,  H01L27/115

摘要： Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate. A floating gate transistor is constituted to include the substrate, source and drain regions, second insulation film, floating gate, third insulation film and control gate. An offset transistor is constituted to include the substrate, source and drain regions, third insulation film and control gate. The first insulation film and the impurity region are used as an element isolation region of a memory cell.

摘要翻译： 在第一导电类型的半导体衬底的表面区域中形成第二导电类型的源区和漏区。 在基板的源极和漏极区域上形成第一绝缘膜。 在位于源区和漏区之间的衬底的该部分上形成具有隧道效应的第二薄绝缘膜。 在第二绝缘膜上形成浮栅。 在第一绝缘膜，浮栅和位于源极和漏极区之间的基板的那部分上形成第三绝缘膜，并且在其上不形成第二绝缘膜。 在第三绝缘膜上以与源极和漏极区相交的方向延伸的条形形成控制栅极。 在除了源极和漏极区域以及位于控制栅极下方的部分之外，在衬底中形成具有比衬底高的杂质浓度的第一导电类型的杂质区域。 浮栅晶体管构成为包括基板，源极和漏极区，第二绝缘膜，浮栅，第三绝缘膜和控制栅。 偏移晶体管构成为包括基板，源极和漏极区域，第三绝缘膜和控制栅极。 第一绝缘膜和杂质区用作存储单元的元件隔离区。

公开(公告)号：US07948350B2

公开(公告)日：2011-05-24

申请号：US12429537

申请日：2009-04-24

申请人： Atsushi Shoji ,  Masatoshi Shindoh

发明人： Atsushi Shoji ,  Masatoshi Shindoh

IPC分类号： H01F27/02 ,  H01F29/06 ,  H01F27/30 ,  H01F17/04 ,  H01F27/08

CPC分类号： H01F3/10 ,  H01F17/045 ,  H01F27/263 ,  H01F27/2828 ,  H01F38/08

摘要： A coil component has a first core with a winding core portion, a second core with a winding core portion, a first coil wound on the winding core portion of the first core, and a second coil wound on the winding core portion of the second core. A part of the first coil is wound on the winding core portion of the second core. The first core and the second core are arranged as magnetically separated from each other.

摘要翻译： 线圈部件具有卷绕芯部的第一芯部，具有卷绕芯部的第二芯部，卷绕在第一芯部的卷绕芯部的第一线圈和缠绕在第二芯部的卷绕芯部的第二线圈 。 第一线圈的一部分缠绕在第二芯的绕组芯部上。 第一芯和第二芯被布置为彼此磁性分离。

公开(公告)号：US20100327353A1

公开(公告)日：2010-12-30

申请号：US12864955

申请日：2009-01-20

申请人： Atsushi Shoji ,  Isao Nakanishi ,  Kazushige Hotta

发明人： Atsushi Shoji ,  Isao Nakanishi ,  Kazushige Hotta

IPC分类号： H01L29/786

CPC分类号： H01L29/78621 ,  H01L29/42384 ,  H01L29/78624 ,  H01L29/78627 ,  H01L29/78645

摘要： A gate electrode 14 of a thin film transistor 100 included in a semiconductor device of the present invention is constituted of a single conductive film. A semiconductor layer 10 includes a first lightly doped impurity region which is provided between the channel region 12 and the source region 15 and which has a lower impurity concentration than those of the source and drain regions 15, and a second lightly doped impurity region which is provided between the channel region 12 and the drain region 15 and which has a lower impurity concentration than those of the source and drain regions 15. The entirety of one of the first and second lightly doped impurity regions (region 16a) extends under the gate electrode, and the other of the first and second lightly doped impurity regions (region 16b) does not extend under the gate electrode.

摘要翻译： 包含在本发明的半导体器件中的薄膜晶体管100的栅电极14由单个导电膜构成。 半导体层10包括第一轻掺杂杂质区，其设置在沟道区12和源极区15之间，其杂质浓度比源极和漏极15的杂质浓度低，第二轻掺杂杂质区为 设置在沟道区12和漏极区15之间，其杂质浓度比源极和漏极区15的杂质浓度低。第一和第二轻掺杂杂质区（区域16a）之一的整体在栅电极 并且第一和第二轻掺杂杂质区域（区域16b）中的另一个不延伸到栅极下方。

公开(公告)号：US20100238258A1

公开(公告)日：2010-09-23

申请号：US12718379

申请日：2010-03-05

申请人： Atsushi Shoji

发明人： Atsushi Shoji

IPC分类号： B41J2/435

CPC分类号： B41J2/473 ,  G03G15/0435 ,  G03G15/5041 ,  G03G2215/0404

摘要： An electrophotographic image forming apparatus performs latent image rendering using a plurality of light sources. The electrophotographic image forming apparatus includes a rendering time control unit that controls a latent image rendering start time for each of the light sources, a scanning time control unit that controls a scanning start time for each of the light sources, a pattern forming unit that forms a pixel pattern corresponding to pixel pattern data defined in advance on a photosensitive member, and a density detection unit that detects a density of the pixel pattern formed on the photosensitive member. The rendering time control unit and the scanning time control unit respectively control the rendering start time and the scanning start time for each of the light sources using a density value detected by the density detection unit.

摘要翻译： 电子照相图像形成装置使用多个光源执行潜像再现。 电子照相图像形成装置包括控制每个光源的潜像渲染开始时间的渲染时间控制单元，控制每个光源的扫描开始时间的扫描时间控制单元，形成 对应于在感光构件上预先定义的像素图案数据的像素图案，以及密度检测单元，其检测形成在感光构件上的像素图案的浓度。 渲染时间控制单元和扫描时间控制单元使用由浓度检测单元检测的浓度值分别控制每个光源的渲染开始时间和扫描开始时间。

公开(公告)号：US06532173B2

公开(公告)日：2003-03-11

申请号：US10101846

申请日：2002-03-21

申请人： Osamu Iioka ,  Naoto Emi ,  Atsushi Shoji ,  Hiroshi Mawatari

发明人： Osamu Iioka ,  Naoto Emi ,  Atsushi Shoji ,  Hiroshi Mawatari

IPC分类号： G11C1604

CPC分类号： G11C16/24 ,  G11C16/0491

摘要： A nonvolatile semiconductor memory device includes a virtual-ground memory array which includes a plurality of nonvolatile memory cells and sub-bit lines connected to the nonvolatile memory cells, first and second selection lines, first and second selection transistors which become conductive in response to activation of the first selection line, a third selection transistor which become conductive in response to activation of the second selection line, a first main bit line which is coupled to and supplies a drain potential to a sub-bit line situated on a drain side of a selected memory cell through the first selection transistor, a second main bit line which is coupled to and supplies a source potential to a sub-bit line situated on a source side of the selected memory cell through one of the second selection transistor and the third selection transistor, and a third main bit line which is coupled to a sub-bit line adjacent to the sub-bit line situated on the drain side of the selected memory cell through another one of the second selection transistor and the third selection transistor, and is coupled to a potential substantially the same as the drain potential.

摘要翻译： 非易失性半导体存储器件包括虚拟地存储器阵列，其包括连接到非易失性存储单元的多个非易失性存储单元和子位线，第一和第二选择线，响应于激活而变为导通的第一和第二选择晶体管 第一选择线的第三选择晶体管，响应于第二选择线的激活而变为导通的第三选择晶体管;第一主位线，其耦合到漏极电位并将其提供给位于漏极侧的子位线 通过第一选择晶体管选择的存储单元，第二主位线，其通过第二选择晶体管和第三选择中的一个耦合到位于所选存储单元的源极侧的子位线并将源极电位提供给源极电位 晶体管和第三主位线，其耦合到与位于选择器的漏极侧的子位线相邻的子位线 通过第二选择晶体管和第三选择晶体管中的另一个，并耦合到与漏极电位基本相同的电位。

公开(公告)号：US5841552A

公开(公告)日：1998-11-24

申请号：US377510

申请日：1995-01-24

申请人： Hiroshi Atobe ,  Atsushi Shoji

发明人： Hiroshi Atobe ,  Atsushi Shoji

IPC分类号： G06K15/02 ,  H04N1/00

CPC分类号： G06K15/02 ,  G06K2215/0002 ,  G06K2215/0011 ,  G06K2215/0071

摘要： An image processing apparatus includes an input device for inputting code, and a conversion device for converting the input code information to pixel information. An output device outputs the pixel information generated by the conversion device to a print unit which is capable of variably adjusting a printing resolution in a predetermined range. A specification device specifies a resolution at which an image corresponding to the input code information is to be printed, in accordance with the input code information. A setting device sets the printing resolution of the print unit as one of positive integer multiples of the specified resolution in the predetermined range.

摘要翻译： 图像处理装置包括用于输入代码的输入装置和用于将输入的代码信息转换为像素信息的转换装置。 输出装置将由转换装置产生的像素信息输出到能够在预定范围内可变地调节打印分辨率的打印单元。 规格装置根据输入的代码信息，指定与输入代码信息对应的图像要被打印的分辨率。 设定装置将打印单元的打印分辨率设置为预定范围内指定分辨率的正整数倍之一。

公开(公告)号：US07843301B2

公开(公告)日：2010-11-30

申请号：US12213783

申请日：2008-06-24

申请人： Atsushi Shoji ,  Makoto Morita ,  Masatoshi Shindoh ,  Masatoshi Ozawa

发明人： Atsushi Shoji ,  Makoto Morita ,  Masatoshi Shindoh ,  Masatoshi Ozawa

IPC分类号： H01F27/29

CPC分类号： H01F17/045 ,  H01F27/022 ,  H01F27/255 ,  H01F27/292 ,  H01F41/005 ,  H01F2017/048 ,  Y10T29/4902

摘要： A coil component having a core including a winding portion, and first and second flanges disposed one on either end of the winding portion, A winding is wound about the winding portion, and first and second terminal electrodes are disposed on the first flange. The first flange has an octagonal shape including a bottom surface, a first peripheral surface, first and third omitted peripheral surfaces disposed one on either side of the first peripheral surface, a second peripheral surface opposing the first peripheral surface, and second and fourth omitted peripheral surfaces disposed one on either side of the second peripheral surface. The first terminal electrode is disposed across the first omitted peripheral surface, a part of the bottom surface in a region connecting the entire first omitted side to the entire third omitted side, and the third omitted peripheral surface. The second terminal electrode is disposed across the second omitted peripheral surface, a part of the bottom surface in a region connecting the entire second omitted side to the entire fourth omitted side, and the fourth omitted peripheral surface. The winding has a first end electrically connected to the first terminal electrode on the first omitted peripheral surface and a second end electrically connected to the second terminal electrode on the second omitted peripheral surface.

摘要翻译： 一种线圈部件，其具有包括绕组部分的芯部，以及设置在绕组部分的任一端上的第一和第二凸缘，绕组绕在绕组部分上，并且第一和第二端子电极设置在第一凸缘上。 第一凸缘具有八边形，包括底面，第一周面，第一和第三省略的外周表面，设置在第一周边表面的任一侧上，第二外周表面和第二和第四省略周边 表面设置在第二周边表面的任一侧上。 第一端子电极跨越第一省略的周边表面，在连接整个第一省略侧和整个第三省略侧的区域中的底部的一部分以及第三省略的周边表面。 第二端子电极跨越第二省略的周边表面，并且在连接整个第二省略侧的整个第四省略侧的区域和第四省略的周边表面中的一部分底面。 绕组具有与第一省略的周面上的第一端子电连接的第一端和在第二省略的外围表面上电连接到第二端子电极的第二端。

公开(公告)号：US20090129804A1

公开(公告)日：2009-05-21

申请号：US12273665

申请日：2008-11-19

申请人： Atsushi Shoji

发明人： Atsushi Shoji

IPC分类号： G03G15/00

CPC分类号： G03G15/043 ,  G03G15/50

摘要： To correct distortion in an optical system of an optical scanning, electrophotographic image generating apparatus, a parallel line group 107′ is printed by a printing apparatus to be calibrated on a sheet on which a correction pattern 101 has been printed. The user reads marker positions to find amounts of deviation of the adjustment pattern from the correction pattern and inputs the amounts of deviation in the printing apparatus. The printing apparatus interpolates values between the input amounts of deviation, establishes positions at which a line in the adjustment pattern deviate one pixel in a sub-scanning direction as scan line changing points and generate new conversion information by pairing the scan line changing points with respective directions of deviation. During image generation, the printing apparatus prints an image by correcting image data according to the conversion information.

摘要翻译： 为了校正光学扫描电子照相图像产生装置的光学系统中的失真，平行线组107'由打印装置打印以在已经印刷有校正图案101的片材上进行校准。 用户读取标记位置以找到调整图案与校正图案的偏差量，并输入打印装置中的偏差量。 打印装置插入输入偏差量之间的值，建立调整图案中的线偏离扫描线变化点的副扫描方向上的一个像素的位置，并通过将扫描线改变点与各自的扫描线对变化点进行配对来生成新的转换信息 偏离方向 在图像生成期间，打印装置根据转换信息通过校正图像数据来打印图像。