公开(公告)号：US09026975B2

公开(公告)日：2015-05-05

申请号：US13800483

申请日：2013-03-13

申请人： Tae-joong Song ,  Pil-un Ko ,  Gyu-hong Kim ,  Jong-hoon Jung

发明人： Tae-joong Song ,  Pil-un Ko ,  Gyu-hong Kim ,  Jong-hoon Jung

IPC分类号： G06F17/50 ,  H01L27/092 ,  H01L27/02

CPC分类号： G06F17/5072 ,  G06F17/50 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/6681

摘要： A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.

摘要翻译： 提供了一种半导体集成电路设计方法及其制造方法，该方法能够最小化由导线，特别是栅极线，半导体集成电路中的开销产生的寄生电容及其制造方法。 一种设计具有FinFET架构的半导体集成电路的方法，包括：对要设计的半导体集成电路进行预仿真; 基于预仿真的结果设计半导体集成电路的部件的布局，所述部件包括第一和第二器件区域以及跨越第一和第二器件区域延伸的第一导电线; 根据至少一个设计规则修改布置在第一和第二设备区域之间并且电切割第一导电线的第一切割区域，以使由第一切割区域产生的第一导电线路的开销最小化。

公开(公告)号：US20080310243A1

公开(公告)日：2008-12-18

申请号：US12155885

申请日：2008-06-11

申请人： Jong-hoon Jung ,  Gyu-hong Kim

发明人： Jong-hoon Jung ,  Gyu-hong Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/12

摘要： A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted through a first bit line and data transmitted through a second bit line in response to a sense amplifier enable signal. The precharge unit may precharge voltage levels of the first bit line and the second bit line to a precharge voltage level in response to a precharge enable signal. The equalizing circuit may be connected to the sense amplifier and the precharge unit and may control the voltage levels of the first bit line and the second bit line to be equal to each other in response to the sense amplifier enable signal. The semiconductor memory device may reduce a time required to perform a precharge operation and/or minimize an increase of the circuit size.

摘要翻译： 提供一种用于减少预充电时间的半导体存储器件。 半导体存储器件可以包括读出放大器，预充电单元和均衡电路。 感测放大器可以响应于读出放大器使能信号来感测和放大通过第一位线传输的数据与通过第二位线传输的数据之间的差异。 预充电单元可以响应于预充电使能信号而将第一位线和第二位线的电压电压预充电到预充电电压电平。 均衡电路可以连接到读出放大器和预充电单元，并且可以响应于读出放大器使能信号而将第一位线和第二位线的电压电平控制为彼此相等。 半导体存储器件可以减少执行预充电操作所需的时间和/或最小化电路尺寸的增加。

公开(公告)号：US07852694B2

公开(公告)日：2010-12-14

申请号：US12155885

申请日：2008-06-11

申请人： Jong-hoon Jung ,  Gyu-hong Kim

发明人： Jong-hoon Jung ,  Gyu-hong Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/12

摘要： A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted through a first bit line and data transmitted through a second bit line in response to a sense amplifier enable signal. The precharge unit may precharge voltage levels of the first bit line and the second bit line to a precharge voltage level in response to a precharge enable signal. The equalizing circuit may be connected to the sense amplifier and the precharge unit and may control the voltage levels of the first bit line and the second bit line to be equal to each other in response to the sense amplifier enable signal. The semiconductor memory device may reduce a time required to perform a precharge operation and/or minimize an increase of the circuit size.

摘要翻译： 提供一种用于减少预充电时间的半导体存储器件。 半导体存储器件可以包括读出放大器，预充电单元和均衡电路。 感测放大器可以响应于读出放大器使能信号来感测和放大通过第一位线传输的数据与通过第二位线传输的数据之间的差异。 预充电单元可以响应于预充电使能信号而将第一位线和第二位线的电压电压预充电到预充电电压电平。 均衡电路可以连接到读出放大器和预充电单元，并且可以响应于读出放大器使能信号而将第一位线和第二位线的电压电平控制为彼此相等。 半导体存储器件可以减少执行预充电操作所需的时间和/或最小化电路尺寸的增加。

公开(公告)号：US20050030805A1

公开(公告)日：2005-02-10

申请号：US10829133

申请日：2004-04-21

申请人： Byung-jae Lee ,  Gyu-hong Kim

发明人： Byung-jae Lee ,  Gyu-hong Kim

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/00

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： When first memory cells connected to a bit line are selected, the bit-line sense amplifier amplifies the voltage levels of the bit line and the complementary bit line using the first current path and the second current path, wherein the first current path is formed between the output node of the sensing enable unit and the bit line in response to the voltage level of the complementary bit line and the first addressing signal, and the second current path is formed between the output node of the sensing enable unit and the complementary bit line in response to the voltage level of the bit line and the second addressing signal.

摘要翻译： 当选择连接到位线的第一存储单元时，位线读出放大器使用第一电流路径和第二电流路径放大位线和互补位线的电压电平，其中第一电流路径形成在 感测使能单元的输出节点和位线响应互补位线和第一寻址信号的电压电平，并且第二电流路径形成在感测使能单元的输出节点和互补位线之间 响应于位线和第二寻址信号的电压电平。

公开(公告)号：US20050057976A1

公开(公告)日：2005-03-17

申请号：US10874604

申请日：2004-06-23

申请人： Jong-doo Joo ,  Gyu-hong Kim

发明人： Jong-doo Joo ,  Gyu-hong Kim

IPC分类号： G11C7/10 ,  H02G3/00

CPC分类号： G11C7/1012 ,  G11C7/1006 ,  G11C2207/104 ,  G11C2207/2227

摘要： Provided are a low power consumption data input/output circuit of an embedded memory device and a data input/output method of the circuit. The embedded memory device includes sub memory cell blocks that share word lines. The data input/output circuit includes input/output lines, bit line sense amplifying unit groups, and data input/output units. Each pair of the input/output lines is arranged in each of the sub memory cell blocks. The bit line sense amplifying unit groups are connected between the sub memory cell blocks and the pairs of input/output lines and mutually transmit data signals between the sub memory cell blocks and the pairs of input/output lines in response to first control signals. Each of the data input/output units is connected to each of input/output line groups each including a first predetermined number of pairs of the input/output lines, selects as a data output path some of the input/output lines included in each of the input/output line groups in response to second control signals, pre-discharges the residual input/output lines to a ground voltage, and receives and transmits the data signals to the sub memory cell blocks via the selected input/output lines.

摘要翻译： 提供了嵌入式存储器件的低功耗数据输入/输出电路和电路的数据输入/输出方法。 嵌入式存储器件包括共享字线的子存储器单元块。 数据输入/输出电路包括输入/​​输出线，位线检测放大单元组和数据输入/输出单元。 每对输入/输出线被布置在每个子存储单元块中。 位线读出放大单元组连接在子存储单元块和输入/输出对之间，并且响应于第一控制信号在子存储单元块和输入/输出对之间相互发送数据信号。 每个数据输入/输出单元连接到每个输入/输出线组，每组输入/输出线组包括第一预定数量的输入/输出线对，选择包括在每个输入/输出线中的一些输入/输出线作为数据输出路径 响应于第二控制信号的输入/输出线路组，将剩余输入/输出线预放电到接地电压，并且经由所选择的输入/输出线接收数据信号并发送到子存储器单元块。

公开(公告)号：US5999463A

公开(公告)日：1999-12-07

申请号：US56426

申请日：1998-04-07

申请人： Youn-sik Park ,  Gyu-hong Kim

发明人： Youn-sik Park ,  Gyu-hong Kim

IPC分类号： H01L27/10 ,  G06F11/00 ,  G11C11/34 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/812 ,  G06F11/00 ,  G11C29/781

摘要： A semiconductor device having a reduced number of column redundancy fuse boxes include a plurality of memory blocks having normal and redundant memory cells, a plurality of normal column selection line drivers, a plurality of redundant column selection line drivers, and a column redundancy fuse box. In particular, the normal and redundant column selection line drivers all include fuses. The column redundancy fuse box is connected in common to the plurality of redundant column selection line drivers. Also, the redundancy fuse box comprises a repair address determining portion for pre-latching a repair address and comparing input addresses with the latched repair address to determine whether the input address is the same as the repair address, and a redundancy enable signal generating portion for generating a redundancy enable signal in response to the output signals of the repair address determining portion.

摘要翻译： 具有减少数量的列冗余熔丝盒的半导体器件包括具有正常和冗余存储单元的多个存储块，多个正常列选择线驱动器，多个冗余列选择线驱动器和列冗余保险丝盒。 特别地，正常和冗余的列选择线驱动器都包括保险丝。 列冗余保险丝盒共同连接到多个冗余列选择线驱动器。 此外，冗余保险丝盒包括修复地址确定部分，用于预先锁定修复地址，并将输入地址与锁存的修复地址进行比较，以确定输入地址是否与修复地址相同;以及冗余使能信号产生部分，用于 响应于修复地址确定部分的输出信号产生冗余使能信号。

公开(公告)号：US6118712A

公开(公告)日：2000-09-12

申请号：US395543

申请日：1999-09-14

申请人： Youn-sik Park ,  Gyu-hong Kim

发明人： Youn-sik Park ,  Gyu-hong Kim

IPC分类号： H01L27/10 ,  G06F11/00 ,  G11C11/34 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/812 ,  G06F11/00 ,  G11C29/781

摘要： A semiconductor device having a reduced number of column redundancy fuse boxes include a plurality of memory blocks having normal and redundant memory cells, a plurality of normal column selection line drivers, a plurality of redundant column selection line drivers, and a column redundancy fuse box. In particular, the normal and redundant column selection line drivers all include fuses. The column redundancy fuse box is connected in common to the plurality of redundant column selection line drivers. Also, the redundancy fuse box comprises a repair address determining portion for pre-latching a repair address and comparing input addresses with the latched repair address to determine whether the input address is the same as the repair address, and a redundancy enable signal generating portion for generating a redundancy enable signal in response to the output signals of the repair address determining portion.

摘要翻译： 具有减少数量的列冗余熔丝盒的半导体器件包括具有正常和冗余存储单元的多个存储块，多个正常列选择线驱动器，多个冗余列选择线驱动器和列冗余保险丝盒。 特别地，正常和冗余的列选择线驱动器都包括保险丝。 列冗余保险丝盒共同连接到多个冗余列选择线驱动器。 此外，冗余保险丝盒包括修复地址确定部分，用于预先锁定修复地址，并将输入地址与锁存的修复地址进行比较，以确定输入地址是否与修复地址相同;以及冗余使能信号产生部分，用于 响应于修复地址确定部分的输出信号产生冗余使能信号。

公开(公告)号：US5926420A

公开(公告)日：1999-07-20

申请号：US1865

申请日：1997-12-31

申请人： Gyu-hong Kim

发明人： Gyu-hong Kim

IPC分类号： G01R31/28 ,  G06F11/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/12 ,  G11C29/48 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00

CPC分类号： G11C29/48

摘要： Merged Memory and Logic (MML) integrated circuits include data path width reducing circuits and methods that are responsive to a test mode signal. In particular, MML circuits include a memory block, a logic block and a first plurality of output data paths that interconnect the memory block and the logic block. A data path width reducing circuit is responsive to a test mode signal, to serially provide output data on the first plurality of output data paths to at least one MML integrated circuit output pad, wherein the number of MML integrated circuit output pads is less than the first plurality. The external data path of the MML integrated circuit is thereby reduced during the test mode. The MML integrated circuit may also include a second plurality of input data paths that interconnect the memory block and the logic block. The data path width reducing circuit also serially provides input data from at least one MML integrated circuit input pad to the second plurality of input data paths wherein the number of MML integrated circuit input pads is less than the second plurality. Preferably, the first and second pluralities are identical and the number of MML integrated circuit input pads and output pads are identical.

摘要翻译： 合并存储和逻辑（MML）集成电路包括响应于测试模式信号的数据路径宽度减小电路和方法。 特别地，MML电路包括存储块，逻辑块和互连存储块和逻辑块的第一多个输出数据路径。 数据路径宽度减小电路响应于测试模式信号，将第一多个输出数据路径上的输出数据串行地提供给至少一个MML集成电路输出焊盘，其中MML集成电路输出焊盘的数量小于 第一个复数。 因此，在测试模式期间，MML集成电路的外部数据路径被减少。 MML集成电路还可以包括互连存储器块和逻辑块的第二多个输入数据路径。 数据路径宽度减小电路还将至少一个MML集成电路输入焊盘的输入数据串行地提供给第二多个输入数据路径，其中MML集成电路输入焊盘的数量小于第二多个。 优选地，第一和第二多个是相同的，并且MML集成电路输入焊盘和输出焊盘的数量是相同的。

公开(公告)号：US07088628B2

公开(公告)日：2006-08-08

申请号：US10829133

申请日：2004-04-21

申请人： Byung-jae Lee ,  Gyu-hong Kim

发明人： Byung-jae Lee ,  Gyu-hong Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： When first memory cells connected to a bit line are selected, the bit-line sense amplifier amplifies the voltage levels of the bit line and the complementary bit line using the first current path and the second current path, wherein the first current path is formed between the output node of the sensing enable unit and the bit line in response to the voltage level of the complementary bit line and the first addressing signal, and the second current path is formed between the output node of the sensing enable unit and the complementary bit line in response to the voltage level of the bit line and the second addressing signal.

摘要翻译： 当选择连接到位线的第一存储单元时，位线读出放大器使用第一电流路径和第二电流路径放大位线和互补位线的电压电平，其中第一电流路径形成在 感测使能单元的输出节点和位线响应互补位线和第一寻址信号的电压电平，并且第二电流路径形成在感测使能单元的输出节点和互补位线之间 响应于位线和第二寻址信号的电压电平。

公开(公告)号：US20050083746A1

公开(公告)日：2005-04-21

申请号：US10959095

申请日：2004-10-07

申请人： Jong-doo Joo ,  Gyu-hong Kim

发明人： Jong-doo Joo ,  Gyu-hong Kim

IPC分类号： G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4094 ,  G11C2207/005

摘要： A sense amplifier includes: a bit line and a complementary bit line; a data input/output line and a complementary data input/output line; first and second transistors which are connected in series between the data input/output line and the bit line; and third and fourth transistors which are connected in series between the complementary data input/output line and the complementary bit line, where the gate of the first transistor is connected to the complementary data input/output line, the gate of the third transistor is connected to the data input/output line, and a write column select line enable signal is input to the gates of the second and fourth transistors. Since the sense amplifier can write data before data of adjacent bit line pairs are amplified in a semiconductor memory device, the write timing can be reduced.

摘要翻译： 读出放大器包括：位线和互补位线; 数据输入/输出线和互补数据输入/输出线; 在数据输入/输出线和位线之间串联连接的第一和第二晶体管; 以及第三和第四晶体管，其串联连接在互补数据输入/输出线和互补位线之间，其中第一晶体管的栅极连接到互补数据输入/输出线，第三晶体管的栅极被连接 到数据输入/输出线，并且写列选择线使能信号被输入到第二和第四晶体管的栅极。 由于读出放大器可以在半导体存储器件中放大相邻位线对的数据之前写入数据，所以可以减少写入定时。