公开(公告)号：US20080310243A1

公开(公告)日：2008-12-18

申请号：US12155885

申请日：2008-06-11

申请人： Jong-hoon Jung ,  Gyu-hong Kim

发明人： Jong-hoon Jung ,  Gyu-hong Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/12

摘要： A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted through a first bit line and data transmitted through a second bit line in response to a sense amplifier enable signal. The precharge unit may precharge voltage levels of the first bit line and the second bit line to a precharge voltage level in response to a precharge enable signal. The equalizing circuit may be connected to the sense amplifier and the precharge unit and may control the voltage levels of the first bit line and the second bit line to be equal to each other in response to the sense amplifier enable signal. The semiconductor memory device may reduce a time required to perform a precharge operation and/or minimize an increase of the circuit size.

摘要翻译： 提供一种用于减少预充电时间的半导体存储器件。 半导体存储器件可以包括读出放大器，预充电单元和均衡电路。 感测放大器可以响应于读出放大器使能信号来感测和放大通过第一位线传输的数据与通过第二位线传输的数据之间的差异。 预充电单元可以响应于预充电使能信号而将第一位线和第二位线的电压电压预充电到预充电电压电平。 均衡电路可以连接到读出放大器和预充电单元，并且可以响应于读出放大器使能信号而将第一位线和第二位线的电压电平控制为彼此相等。 半导体存储器件可以减少执行预充电操作所需的时间和/或最小化电路尺寸的增加。

公开(公告)号：US09026975B2

公开(公告)日：2015-05-05

申请号：US13800483

申请日：2013-03-13

申请人： Tae-joong Song ,  Pil-un Ko ,  Gyu-hong Kim ,  Jong-hoon Jung

发明人： Tae-joong Song ,  Pil-un Ko ,  Gyu-hong Kim ,  Jong-hoon Jung

IPC分类号： G06F17/50 ,  H01L27/092 ,  H01L27/02

CPC分类号： G06F17/5072 ,  G06F17/50 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/6681

摘要： A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.

摘要翻译： 提供了一种半导体集成电路设计方法及其制造方法，该方法能够最小化由导线，特别是栅极线，半导体集成电路中的开销产生的寄生电容及其制造方法。 一种设计具有FinFET架构的半导体集成电路的方法，包括：对要设计的半导体集成电路进行预仿真; 基于预仿真的结果设计半导体集成电路的部件的布局，所述部件包括第一和第二器件区域以及跨越第一和第二器件区域延伸的第一导电线; 根据至少一个设计规则修改布置在第一和第二设备区域之间并且电切割第一导电线的第一切割区域，以使由第一切割区域产生的第一导电线路的开销最小化。

公开(公告)号：US07852694B2

公开(公告)日：2010-12-14

申请号：US12155885

申请日：2008-06-11

申请人： Jong-hoon Jung ,  Gyu-hong Kim

发明人： Jong-hoon Jung ,  Gyu-hong Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/12

摘要： A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted through a first bit line and data transmitted through a second bit line in response to a sense amplifier enable signal. The precharge unit may precharge voltage levels of the first bit line and the second bit line to a precharge voltage level in response to a precharge enable signal. The equalizing circuit may be connected to the sense amplifier and the precharge unit and may control the voltage levels of the first bit line and the second bit line to be equal to each other in response to the sense amplifier enable signal. The semiconductor memory device may reduce a time required to perform a precharge operation and/or minimize an increase of the circuit size.

摘要翻译： 提供一种用于减少预充电时间的半导体存储器件。 半导体存储器件可以包括读出放大器，预充电单元和均衡电路。 感测放大器可以响应于读出放大器使能信号来感测和放大通过第一位线传输的数据与通过第二位线传输的数据之间的差异。 预充电单元可以响应于预充电使能信号而将第一位线和第二位线的电压电压预充电到预充电电压电平。 均衡电路可以连接到读出放大器和预充电单元，并且可以响应于读出放大器使能信号而将第一位线和第二位线的电压电平控制为彼此相等。 半导体存储器件可以减少执行预充电操作所需的时间和/或最小化电路尺寸的增加。

公开(公告)号：US09325980B2

公开(公告)日：2016-04-26

申请号：US13267502

申请日：2011-10-06

申请人： Jong-hoon Jung ,  Dae-sik Kim ,  Kyung-hoon Cha ,  Ho-seop Lee ,  Young-ji Ko

发明人： Jong-hoon Jung ,  Dae-sik Kim ,  Kyung-hoon Cha ,  Ho-seop Lee ,  Young-ji Ko

IPC分类号： G09G3/36 ,  H04N13/04

CPC分类号： H04N13/341 ,  H04N13/398

摘要： A three-dimensional (3D) display panel, a 3D display apparatus using the same, and a driving method thereof are provided. The 3D display apparatus includes: an image display panel which displays an image; a phase shift panel which alternately shifts a polarization direction of light outputted from the image display panel; a backlight unit which provides a backlight; and a control unit which turns off the backlight unit during a crosstalk period where the phase shift panel performs the shift operation and to turn on the backlight unit for a stabilization period after the crosstalk period.

摘要翻译： 提供三维（3D）显示面板，使用其的3D显示装置及其驱动方法。 3D显示装置包括：显示图像的图像显示面板; 相移面板，其交替地偏移从所述图像显示面板输出的光的偏振方向; 提供背光的背光单元; 以及控制单元，其在相移面板执行移位操作的串扰时段期间关闭背光单元，并且在串扰周期之后的稳定时段接通背光单元。

公开(公告)号：US08360591B2

公开(公告)日：2013-01-29

申请号：US12478023

申请日：2009-06-04

申请人： Jong-hoon Jung

发明人： Jong-hoon Jung

IPC分类号： G09F13/04 ,  G09F13/08

CPC分类号： G02F1/133603 ,  G02F1/133608 ,  G02F2001/133612

摘要： Provided is a backlight unit for a liquid crystal display device. The backlight unit includes: a chassis; a printed circuit board connected to a side of the chassis, the printed circuit board including a plurality of light emitting diodes, and a pair of conductive pads through which power is supplied to the light emitting diodes, wherein the pair of conductive pads are disposed on an end of the printed circuit board; and a power socket into which the pair of the conductive pads are inserted.

摘要翻译： 提供了一种用于液晶显示装置的背光单元。 背光单元包括：底盘; 连接到底盘一侧的印刷电路板，印刷电路板包括多个发光二极管，以及一对导电焊盘，通过该导电焊盘向发光二极管供电，其中一对导电焊盘设置在 印刷电路板的一端; 以及插入一对导电垫的电源插座。

公开(公告)号：US06940743B2

公开(公告)日：2005-09-06

申请号：US10864276

申请日：2004-06-09

申请人： Jong-hoon Jung

发明人： Jong-hoon Jung

IPC分类号： G11C11/4096 ,  G11C7/06 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4099 ,  G11C11/00 ,  G11C7/02 ,  G11C11/24

CPC分类号： G11C7/062 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4099

摘要： Semiconductor memory devices are provided which include an array of memory cells, an array of reference cells, and a plurality of sense amplifiers that are associated with respective of the memory cells. The reference cells have a first capacitor that is coupled to a first supply voltage, to a first complementary bit line associated with one of the memory cells and to a second complementary bit line that is associated with a different memory cell. The sense amplifiers are configured to sense and amplify the voltage difference between a signal on the first bit line and a signal on the first complementary bit line. These semiconductor memory devices may output bit cell data without a separate reference voltage generator.

公开(公告)号：US09357207B2

公开(公告)日：2016-05-31

申请号：US12912215

申请日：2010-10-26

申请人： Sang-moo Park ,  Ho-seop Lee ,  Jong-hoon Jung ,  Dae-sik Kim

发明人： Sang-moo Park ,  Ho-seop Lee ,  Jong-hoon Jung ,  Dae-sik Kim

IPC分类号： G09G5/10 ,  H04N13/04 ,  G09G3/36

CPC分类号： H04N13/356 ,  G09G3/36 ,  G09G2320/041 ,  G09G2320/0626 ,  H04N13/398

摘要： Methods and apparatuses are provided for compensating for a temperature of a liquid crystal display (LCD) panel. The method includes selecting a lookup table corresponding to a detected temperature of the LCD panel from among lookup tables for a 3-dimensional (3D) display of the LCD panel; and adjusting luminance to be output to the LCD panel based on the selected lookup table.

摘要翻译： 提供了用于补偿液晶显示（LCD）面板的温度的方法和装置。 该方法包括从用于LCD面板的三维（3D）显示的查找表中选择与LCD面板的检测温度相对应的查找表; 以及基于所选择的查找表来调整要输出到LCD面板的亮度。

公开(公告)号：US09025013B2

公开(公告)日：2015-05-05

申请号：US13097980

申请日：2011-04-29

申请人： Jong-hoon Jung ,  Dae-sik Kim ,  Kyung-hoon Cha ,  Ho-seop Lee ,  Young-ji Ko

发明人： Jong-hoon Jung ,  Dae-sik Kim ,  Kyung-hoon Cha ,  Ho-seop Lee ,  Young-ji Ko

IPC分类号： H04N13/04 ,  H04N9/47 ,  G02B27/22 ,  H04N5/359 ,  G09G3/00 ,  G09G3/20 ,  G09G3/34

CPC分类号： H04N13/341 ,  G02B27/2264 ,  G09G3/003 ,  G09G3/20 ,  G09G3/342 ,  G09G2310/024 ,  G09G2320/0209 ,  H04N5/359 ,  H04N13/344 ,  H04N13/398

摘要： A stereoscopic display apparatus includes a display panel which scans an image at a frame frequency that is an odd-numbered multiple of a field frequency, an image signal input unit which inputs an image signal to the display panel, a backlight unit which emits light to the display panel, and a shutter controller which controls an opening and a closing of a left eye shutter and a right eye shutter of shutter glasses.

摘要翻译： 立体显示装置包括以帧频为奇数倍的图像扫描图像的显示面板，将图像信号输入到显示面板的图像信号输入单元，发出光的背光单元 显示面板和控制快门眼镜的左眼快门和右眼快门的打开和关闭的快门控制器。

公开(公告)号：US20050018470A1

公开(公告)日：2005-01-27

申请号：US10864276

申请日：2004-06-09

申请人： Jong-hoon Jung

发明人： Jong-hoon Jung

IPC分类号： G11C11/4096 ,  G11C7/06 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4099 ,  G11C11/24

CPC分类号： G11C7/062 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4099

摘要： Semiconductor memory devices are provided which include an array of memory cells, an array of reference cells, and a plurality of sense amplifiers that are associated with respective of the memory cells. The reference cells have a first capacitor that is coupled to a first supply voltage, to a first complementary bit line associated with one of the memory cells and to a second complementary bit line that is associated with a different memory cell. The sense amplifiers are configured to sense and amplify the voltage difference between a signal on the first bit line and a signal on the first complementary bit line. These semiconductor memory devices may output bit cell data without a separate reference voltage generator.

摘要翻译： 提供了半导体存储器件，其包括存储器单元阵列，参考单元阵列以及与相应存储器单元相关联的多个读出放大器。 参考单元具有耦合到第一电源电压的第一电容器，与与存储器单元之一相关联的第一互补位线和与不同存储器单元相关联的第二互补位线。 读出放大器被配置为感测和放大第一位线上的信号与第一互补位线上的信号之间的电压差。 这些半导体存储器件可以输出比特单元数据，而不需要单独的参考电压发生器。

公开(公告)号：US08947342B2

公开(公告)日：2015-02-03

申请号：US13025670

申请日：2011-02-11

申请人： Sang-moo Park ,  Jong-hoon Jung ,  Dae-sik Kim

发明人： Sang-moo Park ,  Jong-hoon Jung ,  Dae-sik Kim

IPC分类号： G09G3/36 ,  G09G3/34 ,  G09G3/00

CPC分类号： G09G3/342 ,  G09G3/003 ,  G09G2310/08 ,  G09G2320/064 ,  G09G2360/16

摘要： A method and apparatus for controlling a backlight unit of a three-dimensional (3D) display apparatus receiving a 3D video sequence is provided. The method includes determining the image brightness level of the 3D video sequence displayed on a liquid crystal display (LCD) unit, for each of a plurality of partial regions of the LCD unit to which a plurality of sub-blocks of the backlight unit emit light; determining turn-on times of the plurality of sub-blocks of the backlight unit, based on the image brightness of each of the partial regions of the LCD unit; and determining turn-on periods of the plurality of sub-blocks of the backlight unit by synchronizing with a switching period between a set including a left visual point frame and a right visual point frame of the 3D video sequence.

摘要翻译： 提供了一种用于控制接收3D视频序列的三维（3D）显示装置的背光单元的方法和装置。 该方法包括：确定背光单元的多个子块发光的LCD单元的多个局部区域中的每一个上显示在液晶显示器（LCD）单元上的3D视频序列的图像亮度级别 ; 基于所述LCD单元的每个所述部分区域的图像亮度来确定所述背光单元的所述多个子块的导通时间; 以及通过与包括3D视频序列的左视点和右视点帧的组之间的切换周期同步来确定背光单元的多个子块的接通周期。