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    Inter-connector between unit cells and serial cell
    2.
    发明授权
    Inter-connector between unit cells and serial cell 有权
    单元单元和串行单元之间的连接器

    公开(公告)号：US08404380B2

    公开(公告)日：2013-03-26

    申请号：US12017275

    申请日：2008-01-21

    申请人： Tae-yong Kim

    发明人： Tae-yong Kim

    IPC分类号： H01M2/24

    CPC分类号： H01M2/204 ,  H01M6/42 ,  H01M10/613 ,  H01M10/643 ,  H01M10/6566

    摘要： An inter-connector interposed between two serially connected unit cells provides mechanical strength and conductivity to the serial connection between the unit cells. Embodiments of the inter-connector comprise a supporting frame providing mechanical support for the two unit cells; a welding projection for welding the interconnector to a unit cell; and a welding projection surrounding area located between the welding projection and the supporting frame, wherein the supporting frame is thicker than the welding projection surrounding area, and the welding projection is thicker than the welding projection surrounding area.

    摘要翻译： 插入在两个串联连接的单元电池之间的连接器为单元电池之间的串联连接提供机械强度和导电性。 连接器的实施例包括为两个单元电池提供机械支撑的支撑框架; 用于将互连器焊接到单电池的焊接突起; 以及位于焊接突起和支撑框架之间的焊接突起周围区域，其中支撑框架比焊接突起周围区域厚，并且焊接突起比焊接突起周围区域厚。

    Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines
    4.
    发明授权
    Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines 失效
    具有掩埋位线的半导体器件和具有掩埋位线的半导体器件的制造方法

    公开(公告)号：US07227220B2

    公开(公告)日：2007-06-05

    申请号：US11240544

    申请日：2005-09-30

    申请人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    发明人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    IPC分类号： H01L29/792

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

    摘要翻译： 半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质 所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触 以及与第一线成直角形成并覆盖沟道区的字线。

    Serial interface between unit cells
    5.
    发明授权
    Serial interface between unit cells 有权
    单位单元之间的串行接口

    公开(公告)号：US07758995B2

    公开(公告)日：2010-07-20

    申请号：US12017290

    申请日：2008-01-21

    申请人： Tae-yong Kim ,  Zin Park ,  Seung-il Kim

    发明人： Tae-yong Kim ,  Zin Park ,  Seung-il Kim

    IPC分类号： H01M2/12

    CPC分类号： H01M2/12 ,  H01M2/204 ,  H01M10/613 ,  H01M10/643 ,  H01M10/6562

    摘要： A serial interface interposed between two serially connected unit cells provides mechanical strength to the serial connection and conductive coupling therebetween. The serial interface includes an inter-connector having a first vent hole formed therein configured for conductively coupling an anode outer wall of a first unit cell and a cathode terminal of a second unit cell to each other; and a spacer having a second vent hole formed therein and configured to be disposed between the inter-connector and an anode outer wall of the second unit cell to prevent a short-circuit due to the movement of the inter-connector.

    摘要翻译： 插入在两个串联连接的单元电池之间的串行接口为串联连接提供机械强度并且在它们之间提供导电耦合。 串行接口包括一个连接器，其中形成有第一通气孔，其中构造成将第一单电池的阳极外壁和第二单元电池的阴极端子彼此导电耦合; 以及间隔件，其具有形成在其中的第二通气孔，并且被配置为设置在第二单元电池的连接器间和阳极外壁之间，以防止由于连接器的移动而引起的短路。

    Methods of Manufacturing Semiconductor devices Having Buried Bit Lines
    6.
    发明申请
    Methods of Manufacturing Semiconductor devices Having Buried Bit Lines 审中-公开
    制造埋置位线的半导体器件的方法

    公开(公告)号：US20070190725A1

    公开(公告)日：2007-08-16

    申请号：US11740525

    申请日：2007-04-26

    申请人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    发明人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

    摘要翻译： 半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质 所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触 以及与第一线成直角形成并覆盖沟道区的字线。

    Error correction method and apparatus thereof
    7.
    发明授权
    Error correction method and apparatus thereof 失效
    误差校正方法及其装置

    公开(公告)号：US5315601A

    公开(公告)日：1994-05-24

    申请号：US707811

    申请日：1991-05-30

    申请人： Man-young Lee ,  Hak-song Park ,  Young-cheol Kim ,  Tae-yong Kim ,  Yong-jin Choi ,  Jae-moon Kim

    发明人： Man-young Lee ,  Hak-song Park ,  Young-cheol Kim ,  Tae-yong Kim ,  Yong-jin Choi ,  Jae-moon Kim

    IPC分类号： G06F11/10 ,  H03M13/00 ,  H03M13/15

    CPC分类号： H03M13/15 ,  G06F11/10 ,  H03M13/151

    摘要： An error correction method and apparatus for correcting multiple errors in received digital data word signals calculates syndromes S.sub.0, S.sub.1, S.sub.2 and S.sub.3 from a block of n received data words and a parity check matrix H. First coefficients .sigma..sub.1 and .sigma..sub.2 are calculated from the derived syndromes and a second coefficient K is calculated from the first coefficients .sigma..sub.1 and .sigma..sub.2. An error location value x.sub.1 is calculated from the second coefficient K, actual error location values X.sub.1 and X.sub.2 are calculated from the value x.sub.1, and error values Y.sub.1 and Y.sub.2 are calculated from the actual error location values X.sub.1 and X.sub.2. The received data words are then corrected by applying the calculated error values Y.sub.1 and Y.sub.2. The error location value x.sub.1 calculator is preferably constituted by logic gates which enable the apparatus to be smaller and faster than those using a conventional ROM table.

    摘要翻译： 用于校正接收到的数字数据字信号中的多个误差的纠错方法和装置根据n个接收数据字块和奇偶校验矩阵H来计算校正子S0，S1，S2和S3。首先将系数sigma1和sigma2从 根据第一系数σ1和σ2计算导出的校正子和第二系数K.根据第二系数K计算误差位置值x1，根据值x1计算实际误差位置值X1和X2，并且误差值 Y1和Y2由实际误差位置值X1和X2计算。 然后通过应用计算出的误差值Y1和Y2来校正接收到的数据字。 误差位置值x1计算器优选地由逻辑门构成，使得装置能够比使用常规ROM表的那些更小和更快。

    Multi-bit multi-level non-volatile memory device and methods of operating and fabricating the same
    8.
    发明授权
    Multi-bit multi-level non-volatile memory device and methods of operating and fabricating the same 有权
    多位多级非易失性存储器件及其操作和制造方法

    公开(公告)号：US07602010B2

    公开(公告)日：2009-10-13

    申请号：US11407133

    申请日：2006-04-19

    申请人： Byung-yong Choi ,  Tae-yong Kim ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho ,  Dong-gun Park ,  Choong-ho Lee

    发明人： Byung-yong Choi ,  Tae-yong Kim ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho ,  Dong-gun Park ,  Choong-ho Lee

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851

    摘要： In a non-volatile memory device allowing multi-bit and/or multi-level operations, and methods of operating and fabricating the same, the non-volatile memory device comprises, in one embodiment: a semiconductor substrate, doped with impurities of a first conductivity type, which has one or more fins defined by at least two separate trenches formed in the substrate, the fins extending along the substrate in a first direction; pairs of gate electrodes formed as spacers at sidewalls of the fins, wherein the gate electrodes are insulated from the semiconductor substrate including the fins and extend parallel to the fins; storage nodes between the gate electrodes and the fins, and insulated from the gate electrodes and the semiconductor substrate; source regions and drain regions, which are doped with impurities of a second conductivity type, and are separately formed at least at surface portions of the fins and extend across the first direction of the fins; and channel regions corresponding to the respective gate electrodes, formed at least at surface regions of the sidewalls of the fins between the source and the drain regions.

    摘要翻译： 在允许多位和/或多电平操作的非易失性存储器件及其操作和制造方法中，非易失性存储器件在一个实施例中包括：半导体衬底，掺杂有第一 导电型，其具有由形成在基板中的至少两个分开的沟槽限定的一个或多个散热片，散热片沿第一方向沿着基板延伸; 成对的栅电极在散热片的侧壁处形成为间隔物，其中栅电极与包括散热片的半导体基板绝缘，并平行于翅片延伸; 栅电极和鳍之间的存储节点，并与栅电极和半导体衬底绝缘; 源极区域和漏极区域，其掺杂有第二导电类型的杂质，并且分别形成在鳍片的至少在表面部分并且延伸穿过翅片的第一方向; 以及对应于各个栅电极的沟道区，至少在源极和漏极区之间的翅片的侧壁的表面区域处形成。

    INTER-CONNECTOR BETWEEN UNIT CELLS AND SERIAL CELL
    9.
    发明申请
    INTER-CONNECTOR BETWEEN UNIT CELLS AND SERIAL CELL 有权
    单位细胞和序列细胞之间的连接器

    公开(公告)号：US20080182162A1

    公开(公告)日：2008-07-31

    申请号：US12017275

    申请日：2008-01-21

    申请人： Tae-yong Kim

    发明人： Tae-yong Kim

    IPC分类号： H01M2/10 ,  H01M2/26

    CPC分类号： H01M2/204 ,  H01M6/42 ,  H01M10/613 ,  H01M10/643 ,  H01M10/6566

    摘要： An inter-connector interposed between two serially connected unit cells provides mechanical strength and conductivity to the serial connection between the unit cells. Embodiments of the inter-connector comprise a supporting frame providing mechanical support for the two unit cells; a welding projection for welding the interconnector to a unit cell; and a welding projection surrounding area located between the welding projection and the supporting frame, wherein the supporting frame is thicker than the welding projection surrounding area, and the welding projection is thicker than the welding projection surrounding area.

    摘要翻译： 插入在两个串联连接的单元电池之间的连接器为单元电池之间的串联连接提供机械强度和导电性。 连接器的实施例包括为两个单元电池提供机械支撑的支撑框架; 用于将互连器焊接到单电池的焊接突起; 以及位于焊接突起和支撑框架之间的焊接突起周围区域，其中支撑框架比焊接突起周围区域厚，并且焊接突起比焊接突起周围区域厚。