公开(公告)号：US11355466B2

公开(公告)日：2022-06-07

申请号：US16897296

申请日：2020-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Sen-Kuei Hsu ,  Tin-Hao Kuo ,  Yi-Yang Lei ,  Ying-Cheng Tseng ,  Chi-Hui Lai

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/683

Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.

公开(公告)号：US11239135B2

公开(公告)日：2022-02-01

申请号：US16515024

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Chen ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Tin-Hao Kuo ,  Po-Yuan Teng ,  Chi-Hui Lai

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/3205 ,  H01L25/065 ,  H01L23/373 ,  H01L23/552 ,  H01L23/00 ,  H01L25/18 ,  H01L23/498

Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.

公开(公告)号：US11177192B2

公开(公告)日：2021-11-16

申请号：US16533789

申请日：2019-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Kuo-Chung Yee ,  Tin-Hao Kuo ,  Shih-Wei Chen

IPC: H01L23/473 ,  H01L23/31 ,  H01L23/40 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L21/683

Abstract: A semiconductor device includes a chip package comprising a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die having an active surface, a back surface opposite to the active surface, and a thermal enhancement pattern on the back surface; and a heat dissipation structure connected to the chip package, the heat dissipation structure comprising a heat spreader having a flow channel for a cooling liquid, and the cooling liquid in the flow channel being in contact with the thermal enhancement pattern.

公开(公告)号：US20200243483A1

公开(公告)日：2020-07-30

申请号：US16258677

申请日：2019-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tin-Hao Kuo ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Yu-Chia Lai ,  Po-Yuan Teng

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H05K1/02 ,  H01L25/00

Abstract: A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.

公开(公告)号：US10510686B2

公开(公告)日：2019-12-17

申请号：US15964087

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Hao-Yi Tsai ,  Tin-Hao Kuo ,  Ching-Yao Lin ,  Teng-Yuan Lo ,  Chih Wang

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L25/11

Abstract: A semiconductor package and a manufacturing method thereof are provided with the following steps, attaching a rear surface of a semiconductor die on a first redistribution structure by a die attach material, wherein the semiconductor die is pressed so that the die attach material is extruded laterally out and climbs upwardly to cover a sidewall of the semiconductor die, and after attaching, the die attach material comprises an extruded region surrounding the semiconductor die, a first shortest distance from a midpoint of an bottom edge of semiconductor die to a midpoint of an bottom edge of extruded region in a width direction is greater than a second shortest distance between an endpoint of the bottom edge of semiconductor die to an endpoint of the bottom edge of extruded region; and forming an insulating encapsulant on the first redistribution structure to encapsulate the semiconductor die and the die attach material.

公开(公告)号：US12057405B2

公开(公告)日：2024-08-06

申请号：US17814730

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Kuo Lung Pan ,  Yu-Chia Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/552

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/552 ,  H01L24/16 ,  H01L2224/023 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/16227 ,  H01L2924/3025

Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.

公开(公告)号：US11508665B2

公开(公告)日：2022-11-22

申请号：US16909517

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Kuo Lung Pan ,  Yu-Chia Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/552 ,  H01L21/48

Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.

公开(公告)号：US11282791B2

公开(公告)日：2022-03-22

申请号：US16454086

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Hung-Yi Kuo ,  Hao-Yi Tsai ,  Tin-Hao Kuo ,  Yu-Chia Lai ,  Shih-Wei Chen

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/473 ,  H01L23/36 ,  H01L25/11 ,  H01L25/07 ,  H01L25/065 ,  H01L21/56 ,  H01L21/48 ,  H01L25/075 ,  H01L23/367

Abstract: A semiconductor device includes a first chip package, a heat dissipation structure and an adapter. The first chip package includes a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die has an active surface and a back surface opposite to the active surface. The heat dissipation structure is connected to the chip package. The adapter is disposed over the first chip package and electrically connected to the semiconductor die.

公开(公告)号：US20210398905A1

公开(公告)日：2021-12-23

申请号：US16909517

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Kuo Lung Pan ,  Yu-Chia Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/552 ,  H01L21/48

Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.

公开(公告)号：US20210242159A1

公开(公告)日：2021-08-05

申请号：US16897296

申请日：2020-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Sen-Kuei Hsu ,  Tin-Hao Kuo ,  Yi-Yang Lei ,  Ying-Cheng Tseng ,  Chi-Hui Lai

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L21/48 ,  H01L21/683

Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.