公开(公告)号：US11798940B2

公开(公告)日：2023-10-24

申请号：US16897167

申请日：2020-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pin-Dai Sue ,  Tzung-Yo Hung ,  Jung-Hsuan Chen ,  Ting-Wei Chiang

IPC: H01L21/8238 ,  H01L27/088 ,  H01L23/528 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/528 ,  H01L29/66545

Abstract: A semiconductor device includes a first transistor disposed over a substrate, a second disposed over the first transistor, and a conductive trace. The first transistor includes a first active area extending on a first layer. The second transistor includes a second active area extending on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in a first direction, and the third layer is interposed between the first and second layers. The first active area, the second active area, and the conductive trace overlap in a layout view.

公开(公告)号：US09853035B2

公开(公告)日：2017-12-26

申请号：US14589009

申请日：2015-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsien-Yu Pan ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: H01L27/11 ,  H01L27/02 ,  H01L21/768 ,  H01L27/118

CPC classification number: H01L27/1116 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/11 ,  H01L2027/11887

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

公开(公告)号：US11552085B2

公开(公告)日：2023-01-10

申请号：US17035438

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： You-Cheng Xiao ,  Jhih-Siang Hu ,  Ru-Yu Wang ,  Jung-Hsuan Chen ,  Ting-Wei Chiang

IPC: H01L27/11 ,  H01L23/528

Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.

公开(公告)号：US20200020392A1

公开(公告)日：2020-01-16

申请号：US16583060

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C11/419 ,  H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02 ,  G11C11/412 ,  G11C8/16 ,  G11C7/10

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

公开(公告)号：US10157666B2

公开(公告)日：2018-12-18

申请号：US15871484

申请日：2018-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C8/00 ,  G11C11/419 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11 ,  G11C7/10 ,  G11C8/16 ,  G11C11/412 ,  H01L49/02

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

公开(公告)号：US09466493B2

公开(公告)日：2016-10-11

申请号：US13939201

申请日：2013-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Huei Chen ,  Chien Chi Tien ,  Kao-Cheng Lin ,  Jung-Hsuan Chen

IPC: G01R19/00 ,  H01L21/28 ,  G11C7/06 ,  H01L21/20 ,  H01L27/092

CPC classification number: G11C7/065 ,  G11C11/419 ,  H01L21/20 ,  H01L21/2003 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L23/552 ,  H01L27/0207 ,  H01L27/0296 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649

Abstract: A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.

Abstract translation: 读出放大器（SA）包括具有氧化物定义（OD）区域的半导体衬底，一对SA感测装置，SA使能装置和用于承载SAE信号的读出放大器使能信号（SAE）线。 一对SA感测装置具有与SA使能装置相同的多栅极长度Lg，并且它们都共享相同的OD区域。 当使能时，SAE信号使SA使能装置打开一对SA感测装置中的一个，以从读出放大器读取数据。

公开(公告)号：US12167583B2

公开(公告)日：2024-12-10

申请号：US18064777

申请日：2022-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： You-Cheng Xiao ,  Jhih-Siang Hu ,  Ru-Yu Wang ,  Jung-Hsuan Chen ,  Ting-Wei Chiang

IPC: H10B10/00 ,  H01L23/528

Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.

公开(公告)号：US10991423B2

公开(公告)日：2021-04-27

申请号：US16583039

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C5/06 ,  G11C11/419 ,  G11C7/10 ,  G11C8/16 ,  G11C11/412 ,  H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

公开(公告)号：US09064799B2

公开(公告)日：2015-06-23

申请号：US14079671

申请日：2013-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Huei Chen ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Hung-Jen Liao ,  Li-Chun Tien

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28008 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate.

Abstract translation: 一种方法包括在半导体衬底的有效区域上形成第一多个指状物。 第一多个指状物中的每一个具有在与有源区域的宽度方向平行的方向上延伸的相应长度。 第一多个指状物形成至少一个晶体管的至少一个栅极，该晶体管具有由有源区域的一部分形成的源极和漏极。 第一虚设多晶硅结构形成在第一多个指状物的外部之一和半导体衬底的第一边缘之间的有源区域的一部分上。 第二虚设多晶硅结构在第一虚设多晶硅结构和半导体衬底的第一边缘之间的半导体衬底之上。

公开(公告)号：US10790015B2

公开(公告)日：2020-09-29

申请号：US16583060

申请日：2019-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sahil Preet Singh ,  Jung-Hsuan Chen ,  Yen-Huei Chen ,  Avinash Chander ,  Albert Ying

IPC: G11C5/06 ,  G11C11/419 ,  G11C7/10 ,  G11C8/16 ,  G11C11/412 ,  H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11

Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.