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    CAPPING LAYER FOR GATE ELECTRODES
    1.
    发明申请
    CAPPING LAYER FOR GATE ELECTRODES 有权

    公开(公告)号：US20210057543A1

    公开(公告)日：2021-02-25

    申请号：US16548918

    申请日：2019-08-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chin-Hsiang LIN ,  Teng-Chun TSAI ,  Akira MINEJI ,  Huang-Lin CHAO

    IPC: H01L29/66 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L21/311 ,  H01L21/321

    Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer haying a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

    METHOD FOR MANUFACTURING A FINFET DEVICE
    2.
    发明申请
    METHOD FOR MANUFACTURING A FINFET DEVICE 审中-公开

    公开(公告)号：US20190164963A1

    公开(公告)日：2019-05-30

    申请号：US16053990

    申请日：2018-08-03

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Shen-Nan LEE ,  Kuo-Yin LIN ,  Pin-Chuan SU ,  Teng-Chun TSAI

    IPC: H01L27/088 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/78

    Abstract: A method for manufacturing a semiconductor device is provided. In the method for manufacturing a semiconductor device, at first, a semiconductor substrate of a wafer is etched to form at least one fin. Then, an insulation structure is formed around the fin. Thereafter, the fin is recessed. Then, an epitaxial channel structure is epitaxially grown over the recessed fin. Thereafter, a portion of the epitaxial channel structure over a top surface of the insulation structure is removed. Then, a non-contact-type cleaning operation is performed to clean a top surface of the wafer after removing said portion of the epitaxial channel structure. Thereafter, the top surface of the wafer is cleaned using hydrogen fluoride after removing said portion of the epitaxial channel structure. Then, the insulation structure is recessed, such that the epitaxial channel structure protrudes from the recessed insulation structure.

    MECHANISM FOR MANUFACTURING SEMICONDUCTOR DEVICE
    3.
    发明申请
    MECHANISM FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190103283A1

    公开(公告)日：2019-04-04

    申请号：US16053981

    申请日：2018-08-03

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chen-Hao WU ,  Shen-Nan LEE ,  Chung-Wei HSU ,  Tsung-Ling TSAI ,  Teng-Chun TSAI

    IPC: H01L21/321 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

    Abstract: A method for manufacturing a semiconductor device includes forming a gate electrode over a substrate; forming a hard mask over the gate electrode, in which the hard mask comprises a metal oxide; forming an interlayer dielectric (ILD) layer over the hard mask; forming a contact hole in the ILD layer, wherein the contact hole exposes a source/drain; filling the contact hole with a conductive material; and applying a chemical mechanical polish process to the ILD layer and the conductive material, wherein the chemical mechanical polish process stops at the hard mask, the chemical mechanical polish process uses a slurry containing a boric acid or its derivative, the chemical mechanical polish process has a first removal rate of the ILD layer and a second removal rate of the hard mask, and a first ratio of the first removal rate to the second removal rate is greater than about 5.

    SEMICONDUCTOR DEVICE INCLUDING FIN- FET AND MANUFACTURING METHOD THEREOF
    10.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING FIN- FET AND MANUFACTURING METHOD THEREOF 有权
    包括金属FET及其制造方法的半导体器件

    公开(公告)号：US20160181414A1

    公开(公告)日：2016-06-23

    申请号：US14579708

    申请日：2014-12-22

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Gin-Chen HUANG ,  Tzu-Hsiang HSU ,  Chia-Jung HSU ,  Feng-Cheng YANG ,  Teng-Chun TSAI

    IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/12

    CPC classification number: H01L29/66795 ,  H01L21/762 ,  H01L29/12 ,  H01L29/165 ,  H01L29/511 ,  H01L29/6681 ,  H01L29/785

    Abstract: A semiconductor device includes a first fin structure for a first fin field effect transistor (FET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.

    Abstract translation: 半导体器件包括用于第一鳍式场效应晶体管（FET）的第一鳍结构。 第一鳍结构包括从基板突出的第一基底层，设置在第一基底层上的第一中间层和设置在第一中间层上的第一沟道层。 第一翅片结构还包括由防止下层氧化的材料制成的第一保护层。 第一沟道层由SiGe制成，第一中间层包括设置在第一基极层上的第一半导体（例如，SiGe）层和设置在第一半导体层上的第二半导体层（例如Si）。 第一保护层覆盖第一基底层的侧壁，第一半导体层的侧壁和第二半导体层的侧壁。

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