公开(公告)号：US11723210B2

公开(公告)日：2023-08-08

申请号：US17333300

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu Ching Yang ,  Feng-Cheng Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Chung-Te Lin

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.

公开(公告)号：US11672123B2

公开(公告)日：2023-06-06

申请号：US17168317

申请日：2021-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Jun Wu ,  Yu-Wei Jiang ,  Sheng-Chih Lai

IPC: H01L23/522 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524

CPC classification number: H01L27/1157 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

Abstract: The present disclosure relates to an integrated chip including a three-dimensional memory array. The three-dimensional memory array includes a first local line and a second local line that are elongated vertically, a first memory cell extending between the first local line and the second local line, and a second memory cell directly under the first memory cell, extending between the first local line and the second local line, and coupled in parallel with the first memory cell. The first memory cell is coupled to a first word line and the second memory cell is coupled to a second word line. The first word line and the second word line are elongated horizontally. A first global line is disposed at a first height and is elongated horizontally. A first selector extends vertically from the first local line to the first global line.

公开(公告)号：US20220285395A1

公开(公告)日：2022-09-08

申请号：US17333300

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu Ching Yang ,  Feng-Cheng Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/1159

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.

公开(公告)号：US11723199B2

公开(公告)日：2023-08-08

申请号：US17190735

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu Ching Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H10B51/20 ,  H10B51/30 ,  H10B43/20 ,  H10B43/30

CPC classification number: H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B51/30

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

公开(公告)号：US20220285384A1

公开(公告)日：2022-09-08

申请号：US17190735

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu Ching Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L27/11578 ,  H01L27/11568 ,  H01L27/1159 ,  H01L27/11597

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.