公开(公告)号：US20190164960A1

公开(公告)日：2019-05-30

申请号：US15821970

申请日：2017-11-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Han CHEN ,  Chen-Ming LEE ,  Fu-Kai YANG ,  Mei-Yun WANG ,  Jr-Hung LI ,  Bo-Cyuan LU

IPC分类号： H01L27/088 ,  H01L29/423 ,  H01L21/8234

摘要： A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a first gate structure formed over the fin structure. The FinFET device structure also includes a first capping layer formed over the first gate structure and a first etching stop layer over the first capping layer and the first gate structure. The FinFET device structure further includes a first source/drain (S/D) contact structure formed over the fin structure and adjacent to the first gate structure. A portion of the first etching stop layer which is directly above the first capping layer is higher than another portion of the first etching stop layer which is directly above the first gate spacer layer.

公开(公告)号：US20200043924A1

公开(公告)日：2020-02-06

申请号：US16596209

申请日：2019-10-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Han CHEN ,  Chen-Ming LEE ,  Fu-Kai YANG ,  Mei-Yun WANG ,  Jr-Hung LI ,  Bo-Cyuan LU

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66

摘要： A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure, and a first capping layer formed over the first gate structure. The FinFET device structure includes a first etching stop layer formed over the first capping layer and the first gate structure, and a top surface and a sidewall surface of the first capping layer are in direct contact with the first etching stop layer.

公开(公告)号：US20190131421A1

公开(公告)日：2019-05-02

申请号：US15797973

申请日：2017-10-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiang-Ku SHEN ,  Jin-Mu YIN ,  Tsung-Chieh HSIAO ,  Chia-Lin CHUANG ,  Li-Zhen YU ,  Dian-Hau CHEN ,  Shih-Wei WANG ,  De-Wei YU ,  Chien-Hao CHEN ,  Bo-Cyuan LU ,  Jr-Hung LI ,  Chi-On CHUI ,  Min-Hsiu HUNG ,  Huang-Yi HUANG ,  Chun-Cheng CHOU ,  Ying-Liang CHUANG ,  Yen-Chun HUANG ,  Chih-Tang PENG ,  Cheng-Po CHAU ,  Yen-Ming CHEN

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08

摘要： Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

公开(公告)号：US20190019890A1

公开(公告)日：2019-01-17

申请号：US15646386

申请日：2017-07-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Ting KO ,  Bo-Cyuan LU ,  Jr-Hung LI ,  Chi-On CHUI

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L23/535 ,  H01L29/04 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66

摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a gate structure over the substrate and having a sidewall, a spacer element over the sidewall of the gate structure and a source/drain portion adjacent to the spacer element and the gate structure. The semiconductor device structure also includes an etch stop layer over the source/drain portion, an interlayer dielectric layer over the etch stop layer and in contact with the spacer element, and a contact plug penetrating through the interlayer dielectric layer and the etch stop layer, and electrically connected to the source/drain portion.

公开(公告)号：US20200058793A1

公开(公告)日：2020-02-20

申请号：US16662922

申请日：2019-10-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chung-Ting KO ,  Bo-Cyuan LU ,  Jr-Hung LI ,  Chi-On CHUI

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/04 ,  H01L23/535 ,  H01L21/02 ,  H01L21/768

摘要： A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a gate structure over the substrate. The gate structure has a first sidewall. The method includes forming a spacer element over the first sidewall of the gate structure. The method includes forming a source/drain portion adjacent to the spacer element and the gate structure. The source/drain portion has a first top surface. The method includes depositing an etch stop layer over the first top surface of the source/drain portion. The etch stop layer is made of nitride. The method includes forming a dielectric layer over the etch stop layer. The dielectric layer has a second sidewall and a bottom surface, the etch stop layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the second sidewall.

公开(公告)号：US20190148238A1

公开(公告)日：2019-05-16

申请号：US15833912

申请日：2017-12-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Bo-Cyuan LU ,  Chunyao WANG ,  Jr-Hung LI ,  Chung-Ting KO ,  Chi On Chui

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L27/088

摘要： Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.