公开(公告)号：US20220355437A1

公开(公告)日：2022-11-10

申请号：US17871259

申请日：2022-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Bin HSU ,  Ren-Guei LIN ,  Feng-Inn WU ,  Sheng-Chen WANG ,  Jung-Yu LI

IPC: B24B37/26 ,  B24B57/02 ,  B24B49/10 ,  B24B49/00 ,  B24B49/16

Abstract: A method includes supplying slurry onto a polishing pad; holding a wafer against the polishing pad with a piezoelectric layer interposed vertically between a pressure unit and the wafer; exerting a force on the piezoelectric layer using the pressure unit to make the piezoelectric layer directly press the wafer; generating, using the piezoelectric layer, a first voltage corresponding to a first portion of the wafer and a second voltage corresponding to a second portion of the wafer; tuning the force exerted on the piezoelectric layer according to the first voltage and the second voltage; and polishing, using the polishing pad, the wafer.

公开(公告)号：US20170207095A1

公开(公告)日：2017-07-20

申请号：US14996031

申请日：2016-01-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Hsuan LEE ,  Jyh-Cherng SHEU ,  Sung-Li WANG ,  Cheng-Yu YANG ,  Sheng-Chen WANG ,  Sai-Hooi YEONG

IPC: H01L21/285 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

公开(公告)号：US20170125304A1

公开(公告)日：2017-05-04

申请号：US15242155

申请日：2016-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Chen WANG ,  Kai-Hsuan LEE ,  Sai-Hooi YEONG ,  Chia-Ta YU

IPC: H01L21/8238 ,  H01L29/10 ,  H01L27/092 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/823821 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: In manufacturing a semiconductor device, a stack of first and second semiconductor layers are formed. A fin structure is formed by patterning the first and second semiconductor layers. A cover layer is formed on a bottom part of the fin structure so as to cover side walls of the bottom portion of the fin structure and a bottom part of side walls of the upper portion of the fin structure. An insulating layer is formed so that the fin structure is embedded in the insulating layer. A part of the upper portion is removed so that an opening is formed in the insulating layer. A third semiconductor layer is formed in the opening on the remaining layer of the second semiconductor layer. The insulating layer is recessed so that a part of the third semiconductor layer is exposed from the insulating layer, and a gate structure is formed.

公开(公告)号：US20160218104A1

公开(公告)日：2016-07-28

申请号：US14607971

申请日：2015-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yao WEN ,  Sheng-Chen WANG ,  Sai-Hooi YEONG ,  Hsueh-Chang SUNG ,  Ya-Yun CHENG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/161 ,  H01L29/04 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L21/26513 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an anti-punch through implant (APT) region formed in the fin structure and a barrier layer formed on the APT region. The barrier layer has a middle portion and a peripheral portion, and the middle portion is higher than the peripheral portion. The FinFET device structure further includes an epitaxial layer formed on the barrier layer.

Abstract translation: 提供了一种翅片场设备结构及其形成方法。 FinFET器件结构包括从衬底延伸的衬底和鳍结构。 FinFET器件结构还包括形成在鳍结构中的抗穿通植入（APT）区域和形成在APT区域上的阻挡层。 阻挡层具有中间部分和周边部分，并且中间部分高于周边部分。 FinFET器件结构还包括形成在阻挡层上的外延层。

公开(公告)号：US20170194321A1

公开(公告)日：2017-07-06

申请号：US14987509

申请日：2016-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sai-Hooi YEONG ,  Sheng-Chen WANG ,  Tsung-Yao WEN ,  Yen-Ming CHEN

IPC: H01L27/088 ,  H01L21/223 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/41775 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/7851

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a fin extending along a first direction over a substrate and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and a first insulating gate sidewall on a first lateral surface of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate structure. A portion of the source/drain region extends under the insulating gate sidewall for a substantially constant distance along the first direction.

公开(公告)号：US20160204195A1

公开(公告)日：2016-07-14

申请号：US14592089

申请日：2015-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tsung-Yao WEN ,  Sai-Hooi YEONG ,  Bo-Yu LAI ,  Sheng-Chen WANG

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes a first wire structure formed over the fin structure and a source structure and a drain structure formed at two opposite sides of the fin structure. The semiconductor structure further includes a gate structure formed over the fin structure. In addition, the fin structure and the first wire structure are separated by the gate structure.

Abstract translation: 提供半导体结构及其形成方法。 该半导体结构包括在基板上形成的基板和翅片结构。 半导体结构还包括形成在翅片结构上的第一线结构和形成在翅片结构的两个相对侧处的源极结构和漏极结构。 半导体结构还包括形成在鳍结构上的栅极结构。 此外，鳍结构和第一线结构被栅极结构分开。

公开(公告)号：US20180204726A1

公开(公告)日：2018-07-19

申请号：US15918354

申请日：2018-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yao WEN ,  Sheng-Chen WANG ,  Sai-Hooi YEONG ,  Hsueh-Chang SUNG ,  Ya-Yun CHENG

IPC: H01L21/265 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/161 ,  H01L29/10 ,  H01L21/324 ,  H01L29/04 ,  H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/088

CPC classification number: H01L21/26513 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a protruding structure extending from a substrate and an anti-punch through implant (APT) region formed in the protruding structure. The FinFET device structure includes a barrier layer formed on the APT region, and the barrier layer has a width in a horizontal direction. The width gradually tapers from a bottom of the barrier layer to a top of the barrier layer.

公开(公告)号：US20180083109A1

公开(公告)日：2018-03-22

申请号：US15814129

申请日：2017-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta YU ,  Sheng-Chen WANG ,  Wei-Yuan LU ,  Chien-I KUO ,  Li-Li SU ,  Feng-Cheng YANG ,  Yen-Ming CHEN ,  Sai-Hooi YEONG

IPC: H01L29/24 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/08 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2224/056

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).

公开(公告)号：US20150126095A1

公开(公告)日：2015-05-07

申请号：US14073641

申请日：2013-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yuan-Hsuan CHEN ,  Sheng-Chen WANG ,  Feng-Inn WU

IPC: B24B37/04 ,  B24B37/24 ,  B24B37/10

CPC classification number: B24B37/046 ,  B24B37/105 ,  B24B37/24

Abstract: A chemical mechanical polishing apparatus includes a platen, a polishing head, a magnetizable polishing pad, and an electromagnetic component. The magnetizable polishing pad is disposed between the polishing head and the platen. The electromagnetic component is configured for fastening the magnetizable polishing pad on the platen.

Abstract translation: 化学机械抛光装置包括压板，抛光头，可磁化抛光垫和电磁元件。 可磁化抛光垫设置在抛光头和压板之间。 电磁部件构造成将可磁化抛光垫固定在压板上。

公开(公告)号：US20210035806A1

公开(公告)日：2021-02-04

申请号：US17074110

申请日：2020-10-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Hsuan LEE ,  Jyh-Cherng SHEU ,  Sung-Li WANG ,  Cheng-Yu YANG ,  Sheng-Chen WANG ,  Sai-Hooi YEONG

IPC: H01L21/285 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L21/768

Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.