公开(公告)号：US20150115381A1

公开(公告)日：2015-04-30

申请号：US14068353

申请日：2013-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu CHENG ,  Keng-Yu CHEN ,  Wei-Kung TSAI ,  Kuan-Chi TSAI ,  Tsung-Yu YANG ,  Chung-LONG CHANG ,  Chun-Hung CHEN ,  Chih-Ping CHAO

IPC: H01L27/12 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203

Abstract: Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region.

Abstract translation: 提供了形成集成电路的射频区域的机构的实施例。 集成电路结构的射频区域包括衬底，在衬底上形成的掩埋氧化物层以及形成在衬底和掩埋氧化物层之间的界面层。 集成电路结构的射频区域还包括形成在掩埋氧化物层上的硅层和形成在深沟槽中的层间电介质层。 集成电路结构的射频区域还包括延伸穿过硅层，掩埋氧化物层和界面层的层间电介质层。 集成电路结构的射频区域包括形成在深沟槽中的层间电介质层下方的注入区域和形成在注入区域下方的多晶硅层。

公开(公告)号：US20160099169A1

公开(公告)日：2016-04-07

申请号：US14971031

申请日：2015-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Kuo-Yu CHENG ,  Keng-Yu CHEN ,  Wei-Kung TSAI ,  Kuan-Chi TSAI ,  Tsung-Yu YANG ,  Chung-Long CHANG ,  Chun-Hung CHEN ,  Chih-Ping CHAO

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203

Abstract: The methods for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench.

Abstract translation: 提供了形成集成电路的射频区域的方法。 该方法包括在衬底上形成掩埋氧化物层，并且在衬底和掩埋氧化物层之间形成界面层。 该方法还包括通过掩埋氧化物层和界面层蚀刻以形成深沟槽，并且深沟槽的底表面与界面层的底表面平齐。 该方法还包括在深沟槽的正下方形成植入区域，并在深沟槽中形成层间电介质层。

公开(公告)号：US20150206902A1

公开(公告)日：2015-07-23

申请号：US14158430

申请日：2014-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu CHENG ,  Keng-Yu CHEN ,  Wei-Kung TSAI ,  Kuan-Chi TSAI ,  Tsung-Yu YANG ,  Chung-LONG CHANG ,  Chun-Hung CHEN ,  Chih-Ping CHAO

IPC: H01L27/12 ,  H01L21/306 ,  H01L21/02 ,  H01L21/28 ,  H01L23/66 ,  H01L21/762 ,  H01L27/06 ,  H01L21/311

CPC classification number: H01L27/1203 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/28194 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/84 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/66 ,  H01L27/0629 ,  H01L28/20 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer.

Abstract translation: 提供了用于形成半导体器件结构的实施例。 半导体器件结构包括在衬底上形成的衬底和掩埋氧化物层。 在衬底和掩埋氧化物层之间形成界面层。 半导体器件结构还包括形成在掩埋氧化物层上的硅层; 以及形成在衬底上和深沟槽中的多晶硅层。 多晶硅层延伸穿过硅层，掩埋氧化物层和界面层。

公开(公告)号：US20150020039A1

公开(公告)日：2015-01-15

申请号：US14464730

申请日：2014-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Lung HSUEH ,  Chih-Ping CHAO ,  Chewn-Pu JOU ,  Yung-Chow PENG ,  Harry-Hak-Lay CHUANG ,  Kuo-Tung SUNG

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/50 ,  G06F17/5009 ,  H01L27/088 ,  H01L27/0922

Abstract: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.

Abstract translation: MOS器件包括具有第一和第二触点的有源区。 第一和第二栅极设置在第一和第二触点之间。 第一门被设置成与第一接触相邻并且具有第三接触。 第二栅极被设置成与第二触点相邻并且具有耦合到第三触点的第四触点。 由有源区和第一栅极限定的晶体管具有第一阈值电压，并且由有源区和第二栅极限定的晶体管具有第二阈值电压。