公开(公告)号：US20190006571A1

公开(公告)日：2019-01-03

申请号：US15637900

申请日：2017-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsien TSAI ,  Shang-Ying TSAI ,  Fu-Lung HSUEH ,  Shih-Ming YANG ,  Jheng-Yuan WANG ,  Ming-De CHEN

IPC: H01L35/32 ,  H01L35/34 ,  H01L35/04 ,  H01L35/22

CPC classification number: H01L35/32 ,  H01L35/04 ,  H01L35/22 ,  H01L35/34

Abstract: A semiconductor device includes a substrate; a first thermoelectric conduction leg, disposed on the substrate, and doped with a first type of dopant; a second thermoelectric conduction leg, disposed on the substrate, and doped with a second type of dopant, wherein the first and second thermoelectric conduction legs are spatially spaced from each other but disposed along a common row on the substrate; and a first intermediate thermoelectric conduction structure, disposed on a first end of the second thermoelectric conduction leg, and doped with the first type of dopant.

公开(公告)号：US20140347110A1

公开(公告)日：2014-11-27

申请号：US14456064

申请日：2014-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Fu-Lung HSUEH

IPC: H03L7/10 ,  H03L7/107 ,  H03L7/097

CPC classification number: H03L7/103 ,  H03L7/097 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/18 ,  H03L2207/06

Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

Abstract translation: 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

公开(公告)号：US20140256063A1

公开(公告)日：2014-09-11

申请号：US14280732

申请日：2014-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Lin YANG ,  Jun-De JIN ,  Fu-Lung HSUEH ,  Sa-Lly LIU ,  Tong-Chern ONG ,  Chun-Jung LIN ,  Ya-Chen KAO

IPC: H01L25/065 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01F5/00 ,  H01F27/2804 ,  H01F41/046 ,  H01F2027/2809 ,  H01L23/48 ,  H01L23/5227 ,  H01L2225/06531 ,  H01L2924/0002 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.

Abstract translation: 通信结构包括具有第一线圈的第一半导体衬底和在第一半导体衬底上方具有第二线圈的第二半导体衬底。 第一和第二线圈的内边缘限定在第一线圈下方延伸并在第二线圈之上的体积的边界。 铁磁芯至少部分地位于边界内，使得在第一和第二线圈之间提供互感以在第一和第二线圈之间无线地传输信号或电力。

公开(公告)号：US20140009175A1

公开(公告)日：2014-01-09

申请号：US14020935

申请日：2013-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander KALNITSKY ,  Fu-Lung HSUEH

IPC: G01B7/00

CPC classification number: G01B7/003 ,  A63F13/06 ,  A63F13/211 ,  A63F13/24 ,  A63F2300/1043 ,  A63F2300/105 ,  G01P3/52 ,  G01P15/125 ,  G01P15/16

Abstract: An apparatus for detecting mechanical displacement in a micro-electromechanical system includes a capacitor having first and second plates spaced from one another, the first and second plates having different work functions and being electrically connected with each other. The capacitor plates are movable with respect to one another such that a spacing between the plates changes in response to a force. A current through the capacitor represents a rate of change in the spacing between the plates at a given time.

Abstract translation: 一种用于检测微机电系统中的机械位移的装置包括具有彼此间隔开的第一和第二板的电容器，所述第一和第二板具有不同的功函数并且彼此电连接。 电容器板可以相对于彼此移动，使得板之间的间隔响应于力而变化。 通过电容器的电流表示给定时间间板间距的变化率。

公开(公告)号：US20220386451A1

公开(公告)日：2022-12-01

申请号：US17884418

申请日：2022-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jiun-Yi WU ,  Chien-Hsun LEE ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC: H05K1/02 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

Abstract: An interconnect structure includes a first conductor, a second conductor, a dielectric block, a substrate, and a pair of conductive lines. The first conductor and the second conductor form a differential pair design. The dielectric block surrounds the first conductor and the second conductor. The first conductor is separated from the second conductor by the dielectric block. The substrate surrounds the dielectric block and is spaced apart from the first conductor and the second conductor. The pair of conductive lines is connected to the first conductor and the second conductor, respectively, and extends along a top surface of the dielectric block and a top surface of the substrate.

公开(公告)号：US20210007215A1

公开(公告)日：2021-01-07

申请号：US17025887

申请日：2020-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jiun-Yi WU ,  Chien-Hsun LEE ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC: H05K1/02 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

Abstract: An interconnect structure includes a substrate, a dielectric block, and a conductor. The dielectric block is in the substrate. A dielectric constant of the dielectric block is smaller than a dielectric constant of the substrate, and the dielectric block and the substrate have substantially the same thickness. The conductor includes a first portion extending from a top surface to a bottom surface of the dielectric block and a second portion extending along and contacting the top surface of the dielectric block.

公开(公告)号：US20150249051A1

公开(公告)日：2015-09-03

申请号：US14712940

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming Hsien TSAI ,  Hsieh-Hung HSIEH ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Sa-Lly LIU ,  Fu-Lung HSUEH

IPC: H01L23/522 ,  H03F1/26 ,  H01L23/58 ,  H03F3/04 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5384 ,  H01L23/585 ,  H01L23/645 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/092 ,  H01L28/10 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2924/0002 ,  H03F1/26 ,  H03F3/04 ,  H03F2200/294 ,  H03F2200/372 ,  H01L2924/00

Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract translation: 三维（3D）电路包括包括半导体衬底的第一层，与第一层相邻设置的第二层，包括电感元件部分的三维电感器，电感元件部分包括从第一层延伸到 第二层的介电层。 3D电路包括围绕导电通孔的至少一部分的接地屏蔽。 在一些实施例中，接地屏蔽包括中空圆柱形笼。 在一些实施例中，3D电路是低噪声放大器。

公开(公告)号：US20180027648A1

公开(公告)日：2018-01-25

申请号：US15723099

申请日：2017-10-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jiun-Yi WU ,  Chien-Hsun LEE ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC: H05K1/02 ,  H05K3/42 ,  H05K3/40 ,  H01L23/498 ,  H01L21/48 ,  H01L23/552 ,  H05K1/11 ,  H05K3/00

Abstract: A method for manufacturing an interconnect structure is provided. The method includes the following steps. An opening is through a substrate. A low-k dielectric block is formed in the opening. At least one first via is formed through the low-k dielectric block. A first conductor is formed in the first via.

公开(公告)号：US20170231083A1

公开(公告)日：2017-08-10

申请号：US15016147

申请日：2016-02-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jiun-Yi WU ,  Chien-Hsun LEE ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC: H05K1/02 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/40 ,  H01L21/48 ,  H01L23/552

CPC classification number: H05K1/0216 ,  H01L21/485 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/552 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4007 ,  H05K3/42 ,  H05K3/423 ,  H05K2201/0723 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2201/09645

Abstract: A method for manufacturing an interconnect structure and an interconnect structure are provided. The method includes: forming an opening in a substrate; forming a low-k dielectric block in the opening; forming at least one via in the low-k dielectric block; and forming a conductor in the via. The interconnect structure includes a substrate, a dielectric block, and a conductor. The substrate has an opening therein. The dielectric block is present in the opening of the substrate. The dielectric block has at least one via therein. The dielectric block has a dielectric constant smaller than that of the substrate. The conductor is present in the via of the dielectric block.

公开(公告)号：US20220209093A1

公开(公告)日：2022-06-30

申请号：US17571299

申请日：2022-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsien TSAI ,  Shang-Ying TSAI ,  Fu-Lung HSUEH ,  Shih-Ming YANG ,  Jheng-Yuan WANG ,  Ming-De CHEN

IPC: H01L35/32 ,  H01L35/34 ,  H01L35/04 ,  H01L35/22

Abstract: A semiconductor device includes a substrate; a first thermoelectric conduction leg, disposed on the substrate, and doped with a first type of dopant; a second thermoelectric conduction leg, disposed on the substrate, and doped with a second type of dopant, wherein the first and second thermoelectric conduction legs are spatially spaced from each other but disposed along a common row on the substrate; and a first intermediate thermoelectric conduction structure, disposed on a first end of the second thermoelectric conduction leg, and doped with the first type of dopant.