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    SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS
    1.
    发明申请
    SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS 有权

    公开(公告)号：US20250159857A1

    公开(公告)日：2025-05-15

    申请号：US19024672

    申请日：2025-01-16

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hidehiro FUJIWARA ,  Wei-Min CHAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

    IPC: H10B10/00 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528 ,  H10D89/10

    Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.

    MEMORY DEVICE
    4.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20160284387A1

    公开(公告)日：2016-09-29

    申请号：US14670241

    申请日：2015-03-26

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yen-Huei CHEN ,  Hung-Jen LIAO ,  Chih-Yu LIN ,  Jonathan Tsung-Yung CHANG ,  Wei-Cheng WU

    IPC: G11C7/12 ,  G11C8/08 ,  G11C8/10

    CPC classification number: G11C8/08 ,  G11C11/418

    Abstract: An electronic device is disclosed that includes memory cells, a word line, a selection unit and a self-boosted driver. The memory cells are configured to store data. The word line is coupled to the memory cells. The selection unit is disposed at a first terminal of the word line, and is configured to transmit a selection signal to activate the word line according to one of a read command and a write command. The self-boosted driver is disposed at a second terminal of the word line, and is configured to pull up a voltage level of the word line according to a voltage level of the word line and a control signal.

    Abstract translation: 公开了一种包括存储器单元，字线，选择单元和自增强驱动器的电子设备。 存储单元配置为存储数据。 字线耦合到存储单元。 选择单元设置在字线的第一端子处，并且被配置为根据读取命令和写入命令之一发送选择信号以激活字线。 自升压驱动器设置在字线的第二端子处，并且被配置为根据字线的电压电平和控制信号上拉字线的电压电平。

    STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT
    5.
    发明申请
    STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT 有权

    公开(公告)号：US20220383947A1

    公开(公告)日：2022-12-01

    申请号：US17818386

    申请日：2022-08-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro FUJIWARA ,  Chih-Yu LIN ,  Sahil Preet Singh ,  Hsien-Yu PAN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

    IPC: G11C11/419 ,  G11C11/412

    Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

    SEMICONDUCTOR MEMORY WITH RESPECTIVE POWER VOLTAGES FOR MEMORY CELLS
    7.
    发明申请
    SEMICONDUCTOR MEMORY WITH RESPECTIVE POWER VOLTAGES FOR MEMORY CELLS 审中-公开

    公开(公告)号：US20200381043A1

    公开(公告)日：2020-12-03

    申请号：US16997857

    申请日：2020-08-19

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Cheng WU ,  Chih-Yu LIN ,  Kao-Cheng LIN ,  Wei-Min CHAN ,  Yen-Huei CHEN

    IPC: G11C11/419

    Abstract: A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide a first power voltage via a conductive line for the plurality of first memory cells, and to provide a second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells via the conductive line and for corresponding memory cells of the plurality of second memory cells. A circuit structure of the power circuit is different from a circuit structure of the header circuit.

    MEMORY DEVICE
    9.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20210398986A1

    公开(公告)日：2021-12-23

    申请号：US17035148

    申请日：2020-09-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yi-Hsin NIEN ,  Chih-Yu LIN ,  Wei-Chang ZHAO ,  Hidehiro FUJIWARA

    IPC: H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/8238

    Abstract: A memory device is disclosed. The memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer, and a second portion of the second program line is formed in a third conductive layer above the second conductive layer. A width of at least one of the second portion of the first program line or the second portion of the second program line is different from a width of at least one of the first portion of the first program line or the first portion of the second program line. A method is also disclosed herein.

    SEMICONDUCTOR MEMORY WITH RESPECTIVE POWER VOLTAGES FOR MEMORY CELLS
    10.
    发明申请
    SEMICONDUCTOR MEMORY WITH RESPECTIVE POWER VOLTAGES FOR MEMORY CELLS 审中-公开

    公开(公告)号：US20180277199A1

    公开(公告)日：2018-09-27

    申请号：US15991739

    申请日：2018-05-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Cheng WU ,  Chih-Yu LIN ,  Kao-Cheng LIN ,  Wei-Min CHAN ,  Yen-Huei CHEN

    IPC: G11C11/419

    Abstract: A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit us configured to provide the first power voltage for the plurality of first memory cells, and to provide the second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or the combination thereof, for corresponding memory cells of the plurality of first memory cells and the plurality of second memory cells.

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