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公开(公告)号：US20230371227A1
公开(公告)日：2023-11-16
申请号：US18361384
申请日：2023-07-28
发明人： Yi-Hsin NIEN , Chih-Yu LIN , Wei-Chang ZHAO , Hidehiro FUJIWARA
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522 , H01L21/8238
CPC分类号： H10B10/12 , H01L21/76816 , H01L21/76877 , H01L21/823871 , H01L23/5226 , H01L23/5283
摘要： A memory device includes a first bit cell, a second bit cell, a first word line and a second word line. A first boundary of the second bit cell is adjacent with a first boundary of the first bit cell. The first word line is coupled to the first bit cell. The second word line is coupled to the second bit cell. A first segment of the first word line is overlapped with the first boundary of the second bit cell in a plan view, and a first segment of the second word line is overlapped with a second boundary of the second bit cell in the plan view.
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公开(公告)号：US20160284387A1
公开(公告)日：2016-09-29
申请号：US14670241
申请日：2015-03-26
CPC分类号： G11C8/08 , G11C11/418
摘要： An electronic device is disclosed that includes memory cells, a word line, a selection unit and a self-boosted driver. The memory cells are configured to store data. The word line is coupled to the memory cells. The selection unit is disposed at a first terminal of the word line, and is configured to transmit a selection signal to activate the word line according to one of a read command and a write command. The self-boosted driver is disposed at a second terminal of the word line, and is configured to pull up a voltage level of the word line according to a voltage level of the word line and a control signal.
摘要翻译： 公开了一种包括存储器单元，字线，选择单元和自增强驱动器的电子设备。 存储单元配置为存储数据。 字线耦合到存储单元。 选择单元设置在字线的第一端子处，并且被配置为根据读取命令和写入命令之一发送选择信号以激活字线。 自升压驱动器设置在字线的第二端子处，并且被配置为根据字线的电压电平和控制信号上拉字线的电压电平。
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公开(公告)号：US20220383947A1
公开(公告)日：2022-12-01
申请号：US17818386
申请日：2022-08-09
发明人： Hidehiro FUJIWARA , Chih-Yu LIN , Sahil Preet Singh , Hsien-Yu PAN , Yen-Huei CHEN , Hung-Jen LIAO
IPC分类号： G11C11/419 , G11C11/412
摘要： The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.
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4.发明申请公开(公告)号：US20220359002A1
公开(公告)日：2022-11-10
申请号：US17871635
申请日：2022-07-22
发明人： Yi-Hsin NIEN , Wei-Chang ZHAO , Chih-Yu LIN , Hidehiro FUJIWARA , Yen-Huei CHEN , Ru-Yu WANG
IPC分类号： G11C11/419 , G11C5/06 , G11C11/412
摘要： A memory device includes a first word line and a second word line. A first portion of the first word line is formed in a first metal layer, a second portion of the first word line is formed in a second metal layer above the first metal layer, and a third portion of the first word line is formed in a third metal layer below the second metal layer. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The first portion, the second portion, and the third portion of the first word line have sizes that are different from each other, and the first portion and the second portion of the second word line have sizes that are different from each other.
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公开(公告)号：US20200381043A1
公开(公告)日：2020-12-03
申请号：US16997857
申请日：2020-08-19
发明人： Wei-Cheng WU , Chih-Yu LIN , Kao-Cheng LIN , Wei-Min CHAN , Yen-Huei CHEN
IPC分类号： G11C11/419
摘要： A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide a first power voltage via a conductive line for the plurality of first memory cells, and to provide a second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells via the conductive line and for corresponding memory cells of the plurality of second memory cells. A circuit structure of the power circuit is different from a circuit structure of the header circuit.
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公开(公告)号：US20190393228A1
公开(公告)日：2019-12-26
申请号：US16562299
申请日：2019-09-05
发明人： Hidehiro FUJIWARA , Wei-Min CHAN , Chih-Yu LIN , Yen-Huei CHEN , Hung-Jen LIAO
IPC分类号： H01L27/11 , H01L23/528 , H01L21/768 , H01L21/321
摘要： A device is disclosed that includes a memory bit cell coupled to a bit line, a word line, a pair of metal islands and a pair of connection metal lines. The word line is electrically coupled to the memory bit cell and is elongated in a first direction. The pair of metal islands are disposed at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are elongated in a second direction, and are configured to electrically couple the pair of metal islands to the memory bit cell, respectively. The pair of connection metal lines are separated from the bit line in a layout view. A method of fabricating the device is also provided.
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公开(公告)号：US20210398986A1
公开(公告)日：2021-12-23
申请号：US17035148
申请日：2020-09-28
发明人： Yi-Hsin NIEN , Chih-Yu LIN , Wei-Chang ZHAO , Hidehiro FUJIWARA
IPC分类号： H01L27/11 , H01L23/522 , H01L23/528 , H01L21/768 , H01L21/8238
摘要： A memory device is disclosed. The memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer, and a second portion of the second program line is formed in a third conductive layer above the second conductive layer. A width of at least one of the second portion of the first program line or the second portion of the second program line is different from a width of at least one of the first portion of the first program line or the first portion of the second program line. A method is also disclosed herein.
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公开(公告)号：US20180277199A1
公开(公告)日：2018-09-27
申请号：US15991739
申请日：2018-05-29
发明人： Wei-Cheng WU , Chih-Yu LIN , Kao-Cheng LIN , Wei-Min CHAN , Yen-Huei CHEN
IPC分类号： G11C11/419
摘要： A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit us configured to provide the first power voltage for the plurality of first memory cells, and to provide the second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or the combination thereof, for corresponding memory cells of the plurality of first memory cells and the plurality of second memory cells.
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公开(公告)号：US20230380129A1
公开(公告)日：2023-11-23
申请号：US18362786
申请日：2023-07-31
发明人： Hidehiro FUJIWARA , Wei-Min CHAN , Chih-Yu LIN , Yen-Huei CHEN , Hung-Jen LIAO
IPC分类号： H10B10/00 , H01L27/02 , H01L21/321 , H01L21/768 , H01L23/528
CPC分类号： H10B10/12 , H01L27/0207 , H01L21/321 , H01L21/76838 , H01L23/5283
摘要： A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.
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公开(公告)号：US20210398589A1
公开(公告)日：2021-12-23
申请号：US17035118
申请日：2020-09-28
发明人： Yi-Hsin NIEN , Wei-Chang ZHAO , Chih-Yu LIN , Hidehiro FUJIWARA , Yen-Huei CHEN , Ru-Yu WANG
IPC分类号： G11C11/419 , G11C11/412 , G11C5/06
摘要： A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.
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