公开(公告)号：US20180151500A1

公开(公告)日：2018-05-31

申请号：US15413690

申请日：2017-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao CHEN ,  Chih-Wei LIN ,  Ching-Yao LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4864 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/11 ,  H01L2224/18 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A package structure and methods for forming the same are provided. The package structure includes an integrated circuit die in a package layer. The package structure also includes a first passivation layer covering the package layer and the integrated circuit die, and a second passivation layer over the first passivation layer. The package structure further includes a seed layer and a conductive layer in the second passivation layer. The seed layer covers the top surface of the first passivation layer and extends into the first passivation layer. The conductive layer covers the seed layer and extends into the first passivation layer. In addition, the package structure includes a third passivation layer covering the second passivation layer. The seed layer further extends from the top surface of the first passivation layer to the third passivation layer along a sidewall of the conductive layer.