公开(公告)号：US20190122989A1

公开(公告)日：2019-04-25

申请号：US16222047

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao CHEN ,  Chih-Wei Lin ,  Tsung-Hsien Chiang ,  Ming-Da Cheng ,  Ching-Hua Hsieh

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L25/065

Abstract: A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer over the semiconductor die and the protection layer. The dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the dielectric layer and filling some of the cutting scratches.

公开(公告)号：US20170316957A1

公开(公告)日：2017-11-02

申请号：US15195321

申请日：2016-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shing-Chao CHEN ,  Chih-Wei LIN ,  Meng-Tse CHEN ,  Hui-Min HUANG ,  Ming-Da CHENG ,  Kuo-Lung PAN ,  Wei-Sen CHANG ,  Tin-Hao KUO ,  Hao-Yi TSAI

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/58

CPC classification number: H01L21/566 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/585 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/81

Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes disposing a mold over the carrier substrate. The method further includes forming a protection layer between the mold and the carrier substrate to surround the semiconductor die and the conductive structures. In addition, the method includes removing the mold.

公开(公告)号：US20180151500A1

公开(公告)日：2018-05-31

申请号：US15413690

申请日：2017-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao CHEN ,  Chih-Wei LIN ,  Ching-Yao LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4864 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/11 ,  H01L2224/18 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A package structure and methods for forming the same are provided. The package structure includes an integrated circuit die in a package layer. The package structure also includes a first passivation layer covering the package layer and the integrated circuit die, and a second passivation layer over the first passivation layer. The package structure further includes a seed layer and a conductive layer in the second passivation layer. The seed layer covers the top surface of the first passivation layer and extends into the first passivation layer. The conductive layer covers the seed layer and extends into the first passivation layer. In addition, the package structure includes a third passivation layer covering the second passivation layer. The seed layer further extends from the top surface of the first passivation layer to the third passivation layer along a sidewall of the conductive layer.

公开(公告)号：US20180108613A1

公开(公告)日：2018-04-19

申请号：US15292762

申请日：2016-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao CHEN ,  Chih-Wei LIN ,  Tsung-Hsien CHIANG ,  Ming-Da CHENG ,  Ching-Hua HSIEH

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/18 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/18

Abstract: Structures and formation methods of a chip package are provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes cutting an upper portion of the dielectric layer to improve flatness of the dielectric layer. In addition, the method includes forming a conductive layer over the dielectric layer after cutting the upper portion of the dielectric layer.

公开(公告)号：US20180233382A1

公开(公告)日：2018-08-16

申请号：US15952509

申请日：2018-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shing-Chao CHEN ,  Chih-Wei LIN ,  Meng-Tse CHEN ,  Hui-Min HUANG ,  Ming-Da CHENG ,  Kuo-Lung PAN ,  Wei-Sen CHANG ,  Tin-Hao KUO ,  Hao-Yi TSAI

IPC: H01L21/56 ,  H01L23/58 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L21/566 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/585 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/81

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protection layer encapsulating the semiconductor die. The chip package also includes a conductive structure in the protection layer and separated from the semiconductor die by the protection layer. The chip package further includes an interconnection structure over the conductive structure and the protection layer. The interconnection structure has a protruding portion between the conductive structure and the semiconductor die, and the protruding portion extends into the protection layer.