公开(公告)号：US12035472B2

公开(公告)日：2024-07-09

申请号：US18220026

申请日：2023-07-10

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Akito Yoshida ,  Mahmoud Dreiza ,  Curtis Michael Zwenger

IPC: H05K1/11 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K1/14 ,  H05K1/18 ,  H05K3/30 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40

CPC classification number: H05K1/14 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/10 ,  H01L24/16 ,  H01L24/81 ,  H05K1/11 ,  H05K1/181 ,  H05K1/184 ,  H05K1/185 ,  H05K3/303 ,  H05K3/34 ,  H05K3/363 ,  H05K3/4007 ,  H01L23/3171 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/16055 ,  H01L2224/1607 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/01079 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/10977 ,  H05K2203/043 ,  Y10T29/49165 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A

公开(公告)号：US12002771B2

公开(公告)日：2024-06-04

申请号：US17319641

申请日：2021-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Lung Shih ,  Chao-Keng Li ,  Alan Kuo ,  C. C. Chang ,  Yi-An Lin

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L24/03 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/76837 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/11 ,  H01L2224/0391 ,  H01L2224/1191 ,  H01L2924/30205

Abstract: A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device further includes a dielectric layer over the conductive pad, wherein the dielectric layer has a first conformity. The semiconductor device further includes a passivation layer over the dielectric layer, wherein the passivation layer has a second conformity different from the first conformity.

公开(公告)号：US20240128218A1

公开(公告)日：2024-04-18

申请号：US18156414

申请日：2023-01-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Pin Chang ,  Wei-Cheng Wu ,  Ming-Shih Yeh ,  An-Jhih Su ,  Der-Chyang Yeh

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/3171 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/24 ,  H01L2224/02233 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/06132 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/16147 ,  H01L2224/24146

Abstract: A semiconductor package includes a first semiconductor substrate, an array of conductive bumps, a second semiconductor substrate, and a spacing pattern. The first semiconductor substrate includes a pad region and an array of first pads disposed within the pad region. The array of conductive bumps is disposed on the array of first pads respectively. The second semiconductor substrate is disposed over the first semiconductor substrate and includes an array of second pads bonded to the array of conductive bumps respectively. The spacing pattern is disposed between the first semiconductor substrate and the second semiconductor substrate, wherein the spacing pattern is located at a periphery of the pad region.

公开(公告)号：US11837562B2

公开(公告)日：2023-12-05

申请号：US17224946

申请日：2021-04-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chang-Pin Huang ,  Tung-Liang Shao ,  Hsien-Ming Tu ,  Ching-Jung Yang ,  Yu-Chia Lai

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L24/04 ,  H01L24/11 ,  H01L24/13 ,  H01L24/73 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/0558 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05555 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0615 ,  H01L2224/06051 ,  H01L2224/06154 ,  H01L2224/10126 ,  H01L2224/1134 ,  H01L2224/1191 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/73203 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/3512 ,  H01L2924/01322 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/014 ,  H01L2224/13139 ,  H01L2924/014 ,  H01L2224/13144 ,  H01L2924/014 ,  H01L2224/13147 ,  H01L2924/014 ,  H01L2224/13118 ,  H01L2924/014 ,  H01L2224/13113 ,  H01L2924/014 ,  H01L2224/05111 ,  H01L2924/00014 ,  H01L2224/05572 ,  H01L2924/00012 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/05616 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/01023 ,  H01L2224/05555 ,  H01L2924/00012 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03452 ,  H01L2924/00014 ,  H01L2224/0346 ,  H01L2924/00014 ,  H01L2224/11334 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014

Abstract: Present disclosure provides a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate, a conductive layer in the substrate, a conductive bump over the substrate and electrically coupled to the conductive layer, and a dielectric stack, including a polymer layer laterally surrounding the conductive bump and including a portion spaced from a nearest outer edge of the conductive bump with a gap, wherein a first thickness of the polymer layer in a first region is greater than a second thickness of the polymer layer in a second region adjacent to the first region, a first bottom surface of the polymer layer in the first region is leveled with a second bottom surface of the polymer layer in the second region, and a dielectric layer underneath the polymer layer.

公开(公告)号：US10026717B2

公开(公告)日：2018-07-17

申请号：US15430943

申请日：2017-02-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L23/00 ,  H01L49/02 ,  B81B7/00

CPC classification number: H01L25/0657 ,  B81B7/0074 ,  B81C1/0023 ,  H01L21/4853 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/522 ,  H01L23/5383 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/24 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/0239 ,  H01L2224/0332 ,  H01L2224/0333 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/13184 ,  H01L2224/13565 ,  H01L2224/13616 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/14134 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/24147 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/32145 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48149 ,  H01L2224/4903 ,  H01L2224/73201 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81825 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2224/05 ,  H01L2224/13 ,  H01L2224/81 ,  H01L2224/45099

Abstract: Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

公开(公告)号：US10008413B2

公开(公告)日：2018-06-26

申请号：US14011580

申请日：2013-08-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L21/00 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  B23K26/40 ,  H01L23/31 ,  B23K103/00

CPC classification number: H01L21/78 ,  B23K26/40 ,  B23K2103/50 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/04 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10126 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13184 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Disclosed herein is a method for dicing a wafer, the method comprising forming a molding compound layer over each of one or more dies disposed on a wafer, the one or more dies separated by scribe lines, the molding compound layer having gaps over the respective scribe lines. The wafer is separated into individual dies along the gaps of the molding compound in the scribe lines. Separating the wafer into individual dies comprises cutting at least a portion of the substrate with a laser. Forming the molding compound layer comprises applying a stencil over the one or more dies and using the stencil to form the molding compound layer.

公开(公告)号：US09978656B2

公开(公告)日：2018-05-22

申请号：US13406270

申请日：2012-02-27

Applicant: Tsung-Shu Lin ,  Han-Ping Pu ,  Ming-Da Cheng ,  Chang-Chia Huang ,  Hao-Juin Liu

Inventor： Tsung-Shu Lin ,  Han-Ping Pu ,  Ming-Da Cheng ,  Chang-Chia Huang ,  Hao-Juin Liu

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/293 ,  H01L21/568 ,  H01L23/3157 ,  H01L24/02 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16237 ,  H01L2224/73104 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/207 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures.

公开(公告)号：US09953948B2

公开(公告)日：2018-04-24

申请号：US15363943

申请日：2016-11-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chieh Hsieh ,  Cheng-Lin Huang ,  Po-Hao Tsai ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11616 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13013 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1362 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/16056 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81121 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/384 ,  H01L2924/3841 ,  H01L2924/00014

Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

公开(公告)号：US09935070B2

公开(公告)日：2018-04-03

申请号：US14991426

申请日：2016-01-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Hsiung Lu ,  Hsuan-Ting Kuo ,  Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/768 ,  H01L23/525 ,  H01L23/532 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/11 ,  H01L21/566 ,  H01L21/76885 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02331 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/036 ,  H01L2224/0362 ,  H01L2224/03828 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/10126 ,  H01L2224/1112 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/04953 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.

公开(公告)号：US20170373031A1

公开(公告)日：2017-12-28

申请号：US15582277

申请日：2017-04-28

Applicant: Renesas Electronics Corporation

Inventor： Akira YAJIMA ,  Yoshiaki Yamada

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/311 ,  H01L21/321 ,  H01L21/56 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/06135 ,  H01L2224/10145 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13163 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/16112 ,  H01L2224/16237 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/053

Abstract: The semiconductor device includes: a semiconductor substrate; a conductor layer formed over the semiconductor substrate and having an upper surface and a lower surface; a conductive pillar formed on the upper surface of the conductor layer and having an upper surface, a lower surface, and a sidewall; a protection film covering the upper surface of the conductor layer and having an opening which exposes the upper surface and the sidewall of the conductive pillar; and a protection film covering the sidewall of the conductive pillar. Then, in plan view, the opening of the protection film is wider than the upper surface of the conductive pillar and exposes an entire region of an upper surface of the conductive pillar.