公开(公告)号：US20200381257A1

公开(公告)日：2020-12-03

申请号：US16995223

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung LIN ,  Jung-Hung CHANG ,  Shih-Cheng CHEN ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L21/285 ,  H01L29/66 ,  H01L29/06 ,  H01L29/45 ,  H01L29/78 ,  H01L21/764

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. A top surface of the dielectric fin is close to the epitaxial structure. The semiconductor device structure includes a silicide layer wrapping around the epitaxial structure and partially between the dielectric fin and the epitaxial structure. The silicide layer covers a lower surface of the epitaxial structure, and the lower surface is lower than the top surface of the dielectric fin.

公开(公告)号：US20190067012A1

公开(公告)日：2019-02-28

申请号：US15692221

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An LIN ,  Chun-Hsiung LIN ,  Kai-Hsuan LEE ,  Sai-Hooi YEONG ,  Cheng-Yu YANG ,  Yen-Ting CHEN

IPC: H01L21/285 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate, a gate structure, a first doped structure, a second doped structure, and a dielectric layer. The method includes forming a through hole in the dielectric layer. The method includes performing a physical vapor deposition process to deposit a first metal layer over the first doped structure exposed by the through hole. The method includes reacting the first metal layer with the first doped structure to form a metal semiconductor compound layer between the first metal layer and the first doped structure. The method includes removing the first metal layer. The method includes performing a chemical vapor deposition process to deposit a second metal layer in the through hole. The method includes forming a conductive structure in the through hole and over the second metal layer.

公开(公告)号：US20180174919A1

公开(公告)日：2018-06-21

申请号：US15476068

申请日：2017-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh SU ,  Chih-Hao WANG ,  Jui-Chen HUANG ,  Chun-Hsiung LIN

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/823814 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02639 ,  H01L21/0273 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: A method of forming a semiconductor device includes forming first and second fin structures on a substrate and a patterned polysilicon structure on first portions of the first and second fin structures. The method further includes depositing an insulating layer on second portions of the first and second fin structures and on the patterned polysilicon structure, which may be followed by selectively removing the insulating layer from the second portions and patterning a first hard mask layer on the second portion of the second fin structure. The method also includes growing a first epitaxial region on the second portion of the first fin structure, removing the patterned first hard mask layer from the second portion of the second fin structure, patterning a second hard mask layer on the first epitaxial region, and growing a second epitaxial region on the second portion of the second fin structure.

公开(公告)号：US20220336601A1

公开(公告)日：2022-10-20

申请号：US17853709

申请日：2022-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Cheng CHEN ,  Chun-Hsiung LIN ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L29/40 ,  H01L21/8238 ,  H01L23/522

Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

公开(公告)号：US20200135571A1

公开(公告)日：2020-04-30

申请号：US16284113

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun WANG ,  Chun-Hsiung LIN ,  Chih-Hao WANG ,  Chih-Chao CHOU

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin protruding from a substrate, and forming a disposable mandrel fin on the fin. The method also includes epitaxially growing channel fins on sidewalls of the disposable mandrel fin. The method further includes removing the disposable mandrel fin to form a space between the channel fins, and forming a gate structure to fill the space between the channel fins and to wrap the channel fins. In addition, the method includes forming source and drain structures on opposite sides of the gate structure.

公开(公告)号：US20190131423A1

公开(公告)日：2019-05-02

申请号：US15799385

申请日：2017-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-An LIN ,  Chun-Hsiung LIN ,  Chia-Ta YU ,  Sai-Hooi YEONG ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, a bottom semiconductor fin, at least one sidewall structure, a top semiconductor fin, and a gate structure. The bottom semiconductor fin is disposed on the substrate. The sidewall structure protrudes from the semiconductor fin. The top semiconductor fin is disposed on the bottom semiconductor fin. The top semiconductor fin includes a channel portion and at least one source/drain portion. The source/drain portion is disposed between the channel portion and the sidewall structure. The gate structure covers the channel portion of the top semiconductor fin.

公开(公告)号：US20220352345A1

公开(公告)日：2022-11-03

申请号：US17850850

申请日：2022-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Lun CHEN ,  Bau-Ming WANG ,  Chun-Hsiung LIN

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3115

Abstract: A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin; forming a helmet layer lining the gate structure and the semiconductor fin; etching the helmet layer to remove portions of the helmet layer from opposite sidewalls of the gate structure, wherein the remaining helmet layer comprises a first remaining portion on a top surface of the gate structure and a second remaining portion on a top surface of the semiconductor fin; forming a spacer layer covering the gate structure, wherein the spacer layer is in contact with the first remaining portion and the second remaining portion of the remaining helmet layer; etching the spacer layer and the remaining helmet layer to form gate spacers, wherein each of the gate spacers has a stepped sidewall; and forming source/drain epitaxy structures on opposite sides of the gate structure.

公开(公告)号：US20190067442A1

公开(公告)日：2019-02-28

申请号：US15801171

申请日：2017-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung LIN ,  Chia-Hao CHANG ,  Chih-Hao WANG ,  Wai-Yi LIEN ,  Chih-Chao CHOU ,  Pei-Yu WANG

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/764 ,  H01L29/78

Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.

公开(公告)号：US20200343140A1

公开(公告)日：2020-10-29

申请号：US16924546

申请日：2020-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pei-Hsun WANG ,  Chun-Hsiung LIN ,  Chih-Hao WANG ,  Chih-Chao CHOU

IPC: H01L21/8234 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L21/308

Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a fin protruding from a substrate and forming an isolation structure surrounding the fin. The method also includes epitaxially growing channel fins on sidewalls of the fin over the isolation structure and etching the fin to form a space between the channel fins. The method further includes forming a gate structure to fill the space between the channel fins.

公开(公告)号：US20200273964A1

公开(公告)日：2020-08-27

申请号：US16282214

申请日：2019-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung LIN ,  Pei-Hsun WANG ,  Chih-Hao WANG ,  Kuo-Cheng CHING ,  Jui-Chien HUANG

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure on a substrate, in which the fin structure includes a fin stack of alternating first and second semiconductor layers and forming recesses in the fin stack at source and drain regions. The method also includes etching the second semiconductor layers to form recessed second semiconductor layers, and forming third semiconductor layers on sidewalls of the recessed second semiconductor layers. The method further includes epitaxially growing source and drain structures in the recesses, removing the recessed second semiconductor layers to form spaces between the first semiconductor layers, and oxidizing the third semiconductor layers to form inner spacers. In addition, the method includes forming a gate structure to fill the spaces and to surround the first semiconductor layers.