公开(公告)号：US20200235214A1

公开(公告)日：2020-07-23

申请号：US16838160

申请日：2020-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wen HUANG ,  Chung-Ting KO ,  Hong-Hsien KE ,  Chia-Hui LIN ,  Tai-Chun HUANG

IPC: H01L29/417 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/768 ,  H01L29/45 ,  H01L29/08 ,  H01L29/78

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure, forming a source/drain structure in the fin structure and adjacent to the gate structure, forming a dielectric layer over the gate structure and the source/drain structure, and forming an opening in the dielectric layer to expose the source/drain structure. The method further includes depositing a barrier layer lining a sidewall surface of the opening and a top surface of the source/drain structure. The method further includes etching a portion of the barrier layer to expose the source/drain structure. The method further includes depositing a glue layer covering the sidewall surface of the opening and the source/drain structure in the opening. The method further includes forming a contact structure filling the opening in the dielectric layer. The contact structure is surrounded by the glue layer.

公开(公告)号：US20190019890A1

公开(公告)日：2019-01-17

申请号：US15646386

申请日：2017-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting KO ,  Bo-Cyuan LU ,  Jr-Hung LI ,  Chi-On CHUI

IPC: H01L29/78 ,  H01L21/02 ,  H01L23/535 ,  H01L29/04 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a gate structure over the substrate and having a sidewall, a spacer element over the sidewall of the gate structure and a source/drain portion adjacent to the spacer element and the gate structure. The semiconductor device structure also includes an etch stop layer over the source/drain portion, an interlayer dielectric layer over the etch stop layer and in contact with the spacer element, and a contact plug penetrating through the interlayer dielectric layer and the etch stop layer, and electrically connected to the source/drain portion.

公开(公告)号：US20190157405A1

公开(公告)日：2019-05-23

申请号：US15992619

申请日：2018-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wen HUANG ,  Chung-Ting KO ,  Hong-Hsien KE ,  Chia-Hui LIN ,  Tai-Chun HUANG

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.

公开(公告)号：US20200058793A1

公开(公告)日：2020-02-20

申请号：US16662922

申请日：2019-10-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Ting KO ,  Bo-Cyuan LU ,  Jr-Hung LI ,  Chi-On CHUI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/04 ,  H01L23/535 ,  H01L21/02 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a gate structure over the substrate. The gate structure has a first sidewall. The method includes forming a spacer element over the first sidewall of the gate structure. The method includes forming a source/drain portion adjacent to the spacer element and the gate structure. The source/drain portion has a first top surface. The method includes depositing an etch stop layer over the first top surface of the source/drain portion. The etch stop layer is made of nitride. The method includes forming a dielectric layer over the etch stop layer. The dielectric layer has a second sidewall and a bottom surface, the etch stop layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the second sidewall.

公开(公告)号：US20190148238A1

公开(公告)日：2019-05-16

申请号：US15833912

申请日：2017-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan LU ,  Chunyao WANG ,  Jr-Hung LI ,  Chung-Ting KO ,  Chi On Chui

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L27/088

Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

公开(公告)号：US20190096888A1

公开(公告)日：2019-03-28

申请号：US15874618

申请日：2018-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting KO ,  Jr-Hung LI ,  Chi On CHUI

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/02 ,  H01L21/762 ,  H01L29/423 ,  H01L29/66

Abstract: Methods of forming a differential layer, such as a Contact Etch Stop Layer (CESL), in a semiconductor device are described herein, along with structures formed by the methods. In an embodiment, a structure includes an active area on a substrate, a gate structure over the active area, a gate spacer along a sidewall of the gate structure, and a differential etch stop layer. The differential etch stop layer has a first portion along a sidewall of the gate spacer and has a second portion over an upper surface of the source/drain region. A first thickness of the first portion is in a direction perpendicular to the sidewall of the gate spacer, and a second thickness of the second portion is in a direction perpendicular to the upper surface of the source/drain region. The second thickness is greater than the first thickness.

公开(公告)号：US20170342561A1

公开(公告)日：2017-11-30

申请号：US15169037

申请日：2016-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mo LIN ,  Yi-Hung LIN ,  Jr-Hung LI ,  Tze-Liang LEE ,  Ting-Gang CHEN ,  Chung-Ting KO

IPC: C23C16/455 ,  H01L21/687 ,  C23C16/509 ,  H01J37/32 ,  H01L21/285 ,  H01L21/02

Abstract: A system and method for plasma enhanced deposition processes. An exemplary semiconductor manufacturing system includes a susceptor configured to hold a semiconductor wafer and a sector disposed above the susceptor. The sector includes a first plate and an overlying second plate, operable to form a plasma there between. The first plate includes a plurality of holes extending through the first plate, which vary in at least one of diameter and density from a first region of the first plate to a second region of the first plate.