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    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210305047A1

    公开(公告)日：2021-09-30

    申请号：US17150356

    申请日：2021-01-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jia-Lin WEI ,  Ming-Hui WENG ,  Chih-Cheng LIU ,  Yi-Chen KUO ,  Yen-Yu CHEN ,  Yahru CHENG ,  Jr-Hung LI ,  Ching-Yu CHANG ,  Tze-Liang LEE ,  Chi-Ming YANG

    IPC: H01L21/033 ,  H01L21/308 ,  G03F1/22 ,  G03F7/20

    Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers. The multilayer photoresist structure is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying developer to the selectively exposed multilayer photoresist structure to form the pattern.

    METHOD FOR FORMING SEMICONDUCTOR DEVICE THAT INCLUDES COVERING METAL GATE WITH MULTILAYER DIELECTRIC
    2.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE THAT INCLUDES COVERING METAL GATE WITH MULTILAYER DIELECTRIC 有权

    公开(公告)号：US20210327760A1

    公开(公告)日：2021-10-21

    申请号：US16852191

    申请日：2020-04-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tsai-Jung HO ,  Yu-Shih WANG ,  Tze-Liang LEE

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/321 ,  H01L21/02 ,  H01L21/467

    Abstract: A method includes forming a dummy gate structure over a substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; forming an interlayer dielectric (ILD) layer surrounding the gate spacers; replacing the dummy gate structure with a metal gate structure; etching back the metal gate structure to form a gate trench between the gate spacers; depositing a first dielectric layer in the gate trench, in which the first dielectric layer has horizontal portions over the metal gate structure and the ILD layer, and vertical portions on sidewalls of the gate spacers; etching the vertical portions of the first dielectric layer until the sidewalls of the gate spacers exposed; and performing depositing the first dielectric layer and etching the vertical portions of the first dielectric layer in an alternate manner.

    MULTI-GATE TRANSISTOR STRUCTURE WITH ETCH STOP LAYER
    7.
    发明申请
    MULTI-GATE TRANSISTOR STRUCTURE WITH ETCH STOP LAYER 有权

    公开(公告)号：US20240395881A1

    公开(公告)日：2024-11-28

    申请号：US18791275

    申请日：2024-07-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tze-Liang LEE

    IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

    Abstract: A device includes a gate structure, source/drain regions, a first source/drain contact, an etch stop layer, and a first source/drain via. The gate structure is over a substrate. The source/drain regions are at opposite sides of the gate structure. The first source/drain contact is over a first one of the source/drain regions. The etch stop layer overlaps the gate structure but does not overlap the first source/drain contact. The first source/drain via is over the first source/drain contact. The first source/drain via has a stepped bottom surface structure comprising a lower step in contact with a top surface of the first source/drain contact, an upper step in contact with a top surface of the etch stop layer, and a step rise connecting the lower step and the upper step. The step rise is in contact with a side surface of the etch stop layer.

    CARBON-BASED LINER TO REDUCE CONTACT RESISTANCE
    10.
    发明申请
    CARBON-BASED LINER TO REDUCE CONTACT RESISTANCE 有权

    公开(公告)号：US20240395612A1

    公开(公告)日：2024-11-28

    申请号：US18790273

    申请日：2024-07-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Hsien CHENG ,  Chi-Ming YANG ,  Tze-Liang LEE

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A layer of carbon (e.g., graphite or graphene) at a metal interface (e.g., between an MEOL interconnect and a gate contact or a source or drain region contact, between an MEOL contact plug and a BEOL metallization layer, and/or between BEOL conductive structures) is used to reduce contact resistance at the metal interface, which increases electrical performance of an electronic device. Additionally, in some implementations, the layer of carbon may help prevent heat transfer from a second metal to a first metal when the second metal is deposited over the first metal. This results in more symmetric deposition of the second metal, which reduces surface roughness and contact resistance at the metal interface. As an alternative, in some implementations, the layer of carbon is etched before deposition of the second metal in order to reduce contact resistance at the metal interface.

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