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公开(公告)号:US11380673B2
公开(公告)日:2022-07-05
申请号:US17107694
申请日:2020-11-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wun-Jie Lin , Han-Jen Yang , Yu-Ti Su
IPC: H01L27/02 , H01L29/66 , H02H9/04 , H01L27/088 , H01L29/10 , H01L21/8234 , H01L23/60 , H01L21/28
Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.
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公开(公告)号:US10854595B2
公开(公告)日:2020-12-01
申请号:US16219747
申请日:2018-12-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wun-Jie Lin , Han-Jen Yang , Yu-Ti Su
IPC: H01L27/02 , H01L21/28 , H02H9/04 , H01L27/088 , H01L29/10 , H01L21/8234 , H01L29/66 , H01L23/60
Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.
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公开(公告)号:US20170358569A1
公开(公告)日:2017-12-14
申请号:US15670356
申请日:2017-08-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wun-Jie LIN , Han-Jen Yang , Yu-Ti Su
IPC: H01L27/02 , H01L21/28 , H02H9/04 , H01L29/10 , H01L29/66 , H01L23/60 , H01L21/8234 , H01L27/088
CPC classification number: H01L27/0266 , H01L21/28123 , H01L21/823431 , H01L21/823437 , H01L23/60 , H01L27/0207 , H01L27/0292 , H01L27/0886 , H01L29/1095 , H01L29/66545 , H02H9/046
Abstract: An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.
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公开(公告)号:US12051691B2
公开(公告)日:2024-07-30
申请号:US17020507
申请日:2020-09-14
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Po-Lin Peng , Han-Jen Yang , Jam-Wem Lee , Li-Wei Chu
IPC: H01L27/02 , H01L23/528 , H01L27/07 , H01L29/06 , H01L29/10 , H01L29/861
CPC classification number: H01L27/0277 , H01L23/5286 , H01L27/0722 , H01L29/0649 , H01L29/1083 , H01L29/861
Abstract: An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.
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公开(公告)号:US10777546B2
公开(公告)日:2020-09-15
申请号:US15393723
申请日:2016-12-29
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Po-Lin Peng , Han-Jen Yang , Jam-Wem Lee , Li-Wei Chu
IPC: H01L27/02 , H01L23/528 , H01L27/07 , H01L29/06 , H01L29/10 , H01L29/861
Abstract: An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.
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公开(公告)号:US20190131293A1
公开(公告)日:2019-05-02
申请号:US16219747
申请日:2018-12-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wun-Jie Lin , Han-Jen Yang , Yu-Ti Su
IPC: H01L27/02 , H01L21/28 , H01L23/60 , H01L21/8234 , H01L29/10 , H01L27/088 , H02H9/04 , H01L29/66
Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.
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公开(公告)号:US20210082907A1
公开(公告)日:2021-03-18
申请号:US17107694
申请日:2020-11-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wun-Jie Lin , Han-Jen Yang , Yu-Ti Su
IPC: H01L27/02 , H02H9/04 , H01L27/088 , H01L29/10 , H01L21/8234 , H01L29/66 , H01L23/60 , H01L21/28
Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.
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公开(公告)号:US10157905B2
公开(公告)日:2018-12-18
申请号:US15670356
申请日:2017-08-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wun-Jie Lin , Han-Jen Yang , Yu-Ti Su
IPC: H01L29/66 , H01L27/02 , H01L21/28 , H02H9/04 , H01L27/088 , H01L29/10 , H01L21/8234 , H01L23/60
Abstract: An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.
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