公开(公告)号：US11380673B2

公开(公告)日：2022-07-05

申请号：US17107694

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wun-Jie Lin ,  Han-Jen Yang ,  Yu-Ti Su

IPC: H01L27/02 ,  H01L29/66 ,  H02H9/04 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L23/60 ,  H01L21/28

Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

公开(公告)号：US10854595B2

公开(公告)日：2020-12-01

申请号：US16219747

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wun-Jie Lin ,  Han-Jen Yang ,  Yu-Ti Su

IPC: H01L27/02 ,  H01L21/28 ,  H02H9/04 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/66 ,  H01L23/60

Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

公开(公告)号：US12051896B2

公开(公告)日：2024-07-30

申请号：US18323368

申请日：2023-05-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin Peng ,  Yu-Ti Su ,  Chia-Wei Hsu ,  Ming-Fu Tsai ,  Shu-Yu Su ,  Li-Wei Chu ,  Jam-Wem Lee ,  Chia-Jung Chang ,  Hsiang-Hui Cheng

IPC: H02H9/04 ,  G01R31/00 ,  H02H1/00

CPC classification number: H02H9/046 ,  G01R31/001 ,  H02H1/0007

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.

公开(公告)号：US20220352159A1

公开(公告)日：2022-11-03

申请号：US17867453

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Yao HUANG ,  Yu-Ti Su

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/761

Abstract: The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

公开(公告)号：US10971495B2

公开(公告)日：2021-04-06

申请号：US16591064

申请日：2019-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Yao Huang ,  Wun-Jie Lin ,  Chia-Wei Hsu ,  Yu-Ti Su

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/94 ,  H01L27/02 ,  H01L27/08 ,  H01L29/861

Abstract: A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the first node, and has a gate connected to the second node. A second NMOS transistor has a drain connected to the first node, a gate connected to the first node, and a source connected to the ground or the second node. The first and second PMOS transistors and the first and second NMOS transistors are arranged in the same row. The second PMOS transistor is disposed between the first PMOS transistor and the first and second NMOS transistors.

公开(公告)号：US20190096886A1

公开(公告)日：2019-03-28

申请号：US15881215

申请日：2018-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Yao HUANG ,  Yu-Ti Su

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/74 ,  H01L21/8238

Abstract: The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

公开(公告)号：US11973080B2

公开(公告)日：2024-04-30

申请号：US17867453

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Yao Huang ,  Yu-Ti Su

IPC: H01L27/092 ,  H01L21/761 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L21/74

CPC classification number: H01L27/0921 ,  H01L21/761 ,  H01L21/823892 ,  H01L29/1083 ,  H01L21/74 ,  H01L29/78

Abstract: The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

公开(公告)号：US11929363B2

公开(公告)日：2024-03-12

申请号：US17699493

申请日：2022-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin Peng ,  Li-Wei Chu ,  Ming-Fu Tsai ,  Jam-Wem Lee ,  Yu-Ti Su

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/74 ,  H01L29/86 ,  H01L29/87 ,  H01L23/60 ,  H01L23/62 ,  H01L29/747 ,  H01L29/861

CPC classification number: H01L27/0262 ,  H01L27/0207 ,  H01L27/0255 ,  H01L29/87 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0248 ,  H01L27/0652 ,  H01L27/0658 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/747 ,  H01L29/8611 ,  H01L2924/13034 ,  H01L2924/13035

Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

公开(公告)号：US11355927B2

公开(公告)日：2022-06-07

申请号：US16936236

申请日：2020-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin Peng ,  Yu-Ti Su ,  Chia-Wei Hsu ,  Ming-Fu Tsai ,  Shu-Yu Su ,  Li-Wei Chu ,  Jam-Wem Lee ,  Chia-Jung Chang ,  Hsiang-Hui Cheng

IPC: H02H9/04 ,  G01R31/00 ,  H02H1/00

Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.

公开(公告)号：US10475793B2

公开(公告)日：2019-11-12

申请号：US15495106

申请日：2017-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Yao Huang ,  Wun-Jie Lin ,  Chia-Wei Hsu ,  Yu-Ti Su

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/94 ,  H01L27/02 ,  H01L27/08 ,  H01L29/861

Abstract: A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, having a gate coupled to a second node. A first NMOS transistor coupled between a ground and the second node, having a gate coupled to the first node. A second PMOS transistor, having a drain coupled to the second node, a gate coupled to the second node, and a source coupled to the power supply or the first node. A second NMOS transistor, having a drain coupled to the first node, a gate coupled to the first node, and a source coupled to the ground or the second node.