公开(公告)号：US11063157B1

公开(公告)日：2021-07-13

申请号：US16728452

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Alexander Kalnitsky ,  Shih-Fen Huang ,  Shu-Hui Su ,  Ting-Chen Hsu ,  Tuo-Hsin Chien ,  Felix Ying-Kit Tsui ,  Shi-Min Wu ,  Yu-Chi Chang

IPC: H01L29/94 ,  H01L49/02 ,  H01L23/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/764

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

公开(公告)号：US20190245031A1

公开(公告)日：2019-08-08

申请号：US16387844

申请日：2019-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/027 ,  H01L21/764 ,  H01L23/00 ,  H01L27/108 ,  H01L21/321

CPC classification number: H01L28/91 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/764 ,  H01L23/562 ,  H01L27/016 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/87 ,  H01L28/92 ,  H01L29/66181 ,  H01L29/945 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US20210202711A1

公开(公告)日：2021-07-01

申请号：US17198626

申请日：2021-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Liang-Tai Kuo ,  Yu-Chi Chang

IPC: H01L29/51 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/324

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

公开(公告)号：US20210104598A1

公开(公告)日：2021-04-08

申请号：US17104636

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L27/01 ,  H01L29/94 ,  H01L29/66 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/764 ,  H01L23/00 ,  H01L27/108

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US09178080B2

公开(公告)日：2015-11-03

申请号：US13685029

申请日：2012-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alex Kalnitsky ,  Felix Ying-Kit Tsui ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Jyun-Ying Lin

IPC: H01L29/94 ,  H01L49/02

CPC classification number: H01L29/945 ,  H01L28/91

Abstract: Some embodiments relate to high density capacitor structures. Some embodiments include a semiconductor substrate having an conductive region with a plurality of trenches formed therein. A first dielectric layer is formed over respective bottom portions and respective sidewall portions of the respective trenches. A first conductive layer is formed in the trench and over the first dielectric layer, wherein the first dielectric layer acts as a first capacitor dielectric between the conductive region and the first conductive layer. A second dielectric layer is formed in the trench and over the first conductive layer. A second conductive layer is formed in the trench and over the second dielectric layer, wherein the second dielectric layer acts as a second capacitor dielectric between the first conductive layer and the second conductive layer. Other embodiments are also disclosed.

Abstract translation: 一些实施例涉及高密度电容器结构。 一些实施例包括具有形成在其中的多个沟槽的导电区域的半导体衬底。 第一电介质层形成在相应的底部和相应的沟槽的各个侧壁部分之间。 第一导电层形成在沟槽中并且在第一介电层上方，其中第一介电层用作导电区域和第一导电层之间的第一电容器电介质。 第二电介质层形成在沟槽中并在第一导电层之上。 第二导电层形成在沟槽中并在第二介电层上方，其中第二介电层用作第一导电层和第二导电层之间的第二电容器电介质。 还公开了其他实施例。

公开(公告)号：US20140145299A1

公开(公告)日：2014-05-29

申请号：US13685029

申请日：2012-11-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Alex Kalnitsky ,  Felix Ying-Kit Tsui ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Jyun-Ying Lin

IPC: H01L49/02

CPC classification number: H01L29/945 ,  H01L28/91

Abstract: Some embodiments relate to high density capacitor structures. Some embodiments include a semiconductor substrate having an conductive region with a plurality of trenches formed therein. A first dielectric layer is formed over respective bottom portions and respective sidewall portions of the respective trenches. A first conductive layer is formed in the trench and over the first dielectric layer, wherein the first dielectric layer acts as a first capacitor dielectric between the conductive region and the first conductive layer. A second dielectric layer is formed in the trench and over the first conductive layer. A second conductive layer is formed in the trench and over the second dielectric layer, wherein the second dielectric layer acts as a second capacitor dielectric between the first conductive layer and the second conductive layer. Other embodiments are also disclosed.

Abstract translation: 一些实施例涉及高密度电容器结构。 一些实施例包括具有形成在其中的多个沟槽的导电区域的半导体衬底。 第一电介质层形成在相应的底部和相应的沟槽的各个侧壁部分之间。 第一导电层形成在沟槽中并且在第一介电层上方，其中第一介电层用作导电区域和第一导电层之间的第一电容器电介质。 第二电介质层形成在沟槽中并在第一导电层之上。 第二导电层形成在沟槽中并在第二介电层上方，其中第二介电层用作第一导电层和第二导电层之间的第二电容器电介质。 还公开了其他实施例。

公开(公告)号：US10693019B2

公开(公告)日：2020-06-23

申请号：US16113028

申请日：2018-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Jing-Hwang Yang ,  Ting-Chen Hsu ,  Felix Ying-Kit Tsui ,  Yen-Wen Chen

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/94 ,  H01L29/66

Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high κ dielectric material. By using a high κ material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.

公开(公告)号：US20200035806A1

公开(公告)日：2020-01-30

申请号：US16117166

申请日：2018-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Liang-Tai Kuo ,  Yu-Chi Chang

IPC: H01L29/51 ,  H01L21/3115 ,  H01L21/324 ,  H01L29/66

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

公开(公告)号：US10529818B1

公开(公告)日：2020-01-07

申请号：US16117166

申请日：2018-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Liang-Tai Kuo ,  Yu-Chi Chang

IPC: H01L21/8234 ,  H01L29/51 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/324

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

公开(公告)号：US10276651B2

公开(公告)日：2019-04-30

申请号：US15694218

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/764 ,  H01L23/00 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/306

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.