公开(公告)号：US10693019B2

公开(公告)日：2020-06-23

申请号：US16113028

申请日：2018-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Jing-Hwang Yang ,  Ting-Chen Hsu ,  Felix Ying-Kit Tsui ,  Yen-Wen Chen

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/94 ,  H01L29/66

Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high κ dielectric material. By using a high κ material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.

公开(公告)号：US10276651B2

公开(公告)日：2019-04-30

申请号：US15694218

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/764 ,  H01L23/00 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/306

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US11063157B1

公开(公告)日：2021-07-13

申请号：US16728452

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Alexander Kalnitsky ,  Shih-Fen Huang ,  Shu-Hui Su ,  Ting-Chen Hsu ,  Tuo-Hsin Chien ,  Felix Ying-Kit Tsui ,  Shi-Min Wu ,  Yu-Chi Chang

IPC: H01L29/94 ,  H01L49/02 ,  H01L23/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/764

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

公开(公告)号：US20190245031A1

公开(公告)日：2019-08-08

申请号：US16387844

申请日：2019-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/027 ,  H01L21/764 ,  H01L23/00 ,  H01L27/108 ,  H01L21/321

CPC classification number: H01L28/91 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/764 ,  H01L23/562 ,  H01L27/016 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/87 ,  H01L28/92 ,  H01L29/66181 ,  H01L29/945 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US20160020267A1

公开(公告)日：2016-01-21

申请号：US14867723

申请日：2015-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin

IPC: H01L49/02

CPC classification number: H01L28/91 ,  H01L29/945

Abstract: Some embodiments relate to high density capacitor structures. Some embodiments include a first trench capacitor, a second trench capacitor and an interconnect structure. The first trench capacitor includes a first capacitor plate disposed in a plurality of trenches in a semiconductor substrate, and a second capacitor plate disposed in the plurality of trenches and separated from the first capacitor plate by a first capacitor dielectric along bottom and sidewall surfaces of the plurality of trenches. The second trench capacitor is disposed over the first trench capacitor. The second trench capacitor includes the second capacitor plate, and a third capacitor plate disposed in the plurality of trenches and separated from the second capacitor plate by a second capacitor dielectric. The interconnect structure connects the first capacitor plate and the third capacitor plate such that the first and second trench capacitors are in parallel.

Abstract translation: 一些实施例涉及高密度电容器结构。 一些实施例包括第一沟槽电容器，第二沟槽电容器和互连结构。 第一沟槽电容器包括设置在半导体衬底中的多个沟槽中的第一电容器板和设置在多个沟槽中的第二电容器板，并且通过第一电容器电介质沿第一电容器电介质沿第一电容器电介质的底部和侧壁表面分离 多个沟渠。 第二沟槽电容器设置在第一沟槽电容器上。 第二沟槽电容器包括第二电容器板和设置在多个沟槽中并且通过第二电容器电介质与第二电容器板分离的第三电容器板。 互连结构连接第一电容器板和第三电容器板，使得第一和第二沟槽电容器是并联的。

公开(公告)号：US20230361166A1

公开(公告)日：2023-11-09

申请号：US18341498

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L29/94 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/764 ,  H01L21/321 ,  H01L27/01 ,  H01L21/3213 ,  H01L23/00 ,  H01L21/027 ,  H01L21/3205 ,  H01L29/66 ,  H01L27/08

CPC classification number: H01L28/91 ,  H10B12/37 ,  H01L21/31111 ,  H01L28/87 ,  H01L21/31053 ,  H01L21/30604 ,  H01L21/764 ,  H01L21/3212 ,  H01L27/016 ,  H01L21/32133 ,  H10B12/0387 ,  H01L29/945 ,  H01L28/92 ,  H01L23/562 ,  H01L21/0274 ,  H01L21/32055 ,  H01L29/66181 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2924/19105 ,  H01L27/0805 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/13101 ,  H01L2924/1304 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2224/48227 ,  H01L2924/19011 ,  H01L2924/19103 ,  H01L2224/73204 ,  H01L2224/48091 ,  H01L2924/13091 ,  H01L2924/1305 ,  H01L2924/00014 ,  H01L2224/32145

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US11688762B2

公开(公告)日：2023-06-27

申请号：US17104636

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/306 ,  H01L27/01 ,  H01L29/94 ,  H01L29/66 ,  H10B12/00 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/764 ,  H01L23/00 ,  H01L27/08

CPC classification number: H01L28/91 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/764 ,  H01L23/562 ,  H01L27/016 ,  H01L28/87 ,  H01L28/92 ,  H01L29/66181 ,  H01L29/945 ,  H10B12/0387 ,  H10B12/37 ,  H01L27/0805 ,  H01L2224/13101 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/1305 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/00012

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US20210202761A1

公开(公告)日：2021-07-01

申请号：US16728452

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Alexander Kalnitsky ,  Shih-Fen Huang ,  Shu-Hui Su ,  Ting-Chen Hsu ,  Tuo-Hsin Chien ,  Felix Ying-Kit Tsui ,  Shi-Min Wu ,  Yu-Chi Chang

IPC: H01L29/94 ,  H01L49/02 ,  H01L23/00 ,  H01L21/764 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

公开(公告)号：US20190074349A1

公开(公告)日：2019-03-07

申请号：US15694218

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/764 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/108 ,  H01L23/00

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US20210104598A1

公开(公告)日：2021-04-08

申请号：US17104636

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L27/01 ,  H01L29/94 ,  H01L29/66 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/764 ,  H01L23/00 ,  H01L27/108

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.