公开(公告)号：US20230411307A1

公开(公告)日：2023-12-21

申请号：US17841275

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yi Lin ,  Kuang-Chun Lee ,  Chien-Chen Li ,  Chien-Li Kuo ,  Kuo-Chio Liu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L23/3185 ,  H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a large package component, such as a CoWoS, adhered to a large package substrate, such as a printed circuit board, an underfill material disposed between the large package component and the large package substrate, and a stress-release structure with high elongation values formed from photolithography encapsulated by the underfill material. The stress-release structure helping to reduce stress in the underfill material to reduce the risk of underfill cracking caused by the difference in coefficients of thermal expansion between the large package component and the large package substrate.

公开(公告)号：US20230377905A1

公开(公告)日：2023-11-23

申请号：US17751234

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Li Kuo ,  Chien-Chen Li ,  Kuo-Chio Liu ,  Kuang-Chun Lee ,  Wen-Yi Lin

IPC: H01L21/48 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/486 ,  H01L23/481 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/73 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/15311 ,  H01L2224/73267

Abstract: In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.

公开(公告)号：US10312207B2

公开(公告)日：2019-06-04

申请号：US15883797

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/31 ,  H01L23/29

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

公开(公告)号：US10276651B2

公开(公告)日：2019-04-30

申请号：US15694218

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/764 ,  H01L23/00 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/306

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US09941384B2

公开(公告)日：2018-04-10

申请号：US14839931

申请日：2015-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jheng-Sheng You ,  Hsin-Chih Lin ,  Kun-Ming Huang ,  Lieh-Chuan Chen ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L21/50 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/66462 ,  H01L29/1066 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/452 ,  H01L29/7786

Abstract: A semiconductor device includes a first III-V compound layer on a substrate, a second III-V compound layer on the first III-V compound layer, in which a material of the first III-V compound layer is different from that of the second III-V compound layer, a gate metal stack disposed on the second III-V compound layer, a source contact and a drain contact disposed at opposite sides of the gate metal stack, a gate field plate disposed between the gate metal stack and the drain contact, an anti-reflective coating (ARC) layer formed on the source contact and the drain contact, and an etch stop layer formed on the ARC layer.

公开(公告)号：US20230387101A1

公开(公告)日：2023-11-30

申请号：US17828310

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Haw Tsao ,  Chien-Li Kuo ,  Kuo-Chio Liu

IPC: H01L25/00 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/60 ,  H01L2021/6006

Abstract: In an embodiment, a method of forming an integrated circuit package includes: attaching a first carrier to a package component, the package component comprising: an interposer; a first semiconductor die attached to a first side of the interposer; a second semiconductor die attached to the first side of the interposer; an encapsulant encapsulating the first semiconductor die and the second semiconductor die; and conductive connectors attached to a second side of the interposer; attaching a second carrier to a package substrate, the package substrate comprising bond pads; bonding the conductive connectors of the package component to the bond pads of the package substrate by reflowing the conductive connectors while the first carrier is attached to the package component and while the second carrier is attached to the package substrate; removing the first carrier; and removing the second carrier.

公开(公告)号：US11621235B2

公开(公告)日：2023-04-04

申请号：US17363717

申请日：2021-06-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuen-Shian Chen ,  Chien-Li Kuo

IPC: H01L23/58 ,  H01L23/532 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31

Abstract: Structures and methods for reducing thermal expansion mismatch during chip scale packaging are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes a first metal layer over a substrate, a dielectric region, and a polymer region. The first metal layer comprises a first device metal structure. The dielectric region is formed over the first metal layer. The polymer region is formed over the dielectric region. The dielectric region comprises a plurality of metal layers and an inter-metal dielectric layer comprising dielectric material between each pair of two adjacent metal layers in the plurality of metal layers. Each of the plurality of metal layers comprises a dummy metal structure over the first device metal structure. The dummy metal structures in each pair of two adjacent metal layers in the plurality of metal layers shield respectively two non-overlapping portions of the first device metal structure from a top view of the semiconductor structure.

公开(公告)号：US11515398B2

公开(公告)日：2022-11-29

申请号：US17005513

申请日：2020-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Li Kuo ,  Scott Liu ,  Po-Wei Chen ,  Shih-Hsiang Tai

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10

Abstract: The present disclosure relates to a transistor device having source and drain regions within a substrate. A gate electrode is between the source and drain regions. A spacer has a lower lateral portion along an upper surface of the substrate between the gate electrode and the drain region, a vertical portion extending along a sidewall of the gate electrode, and an upper lateral portion extending from the vertical portion to an outermost sidewall directly over the gate electrode. A field plate is disposed along an upper surface and a sidewall of the spacer and is separated from the gate electrode and the substrate by the spacer. A first ILD layer overlies the substrate, the gate electrode, and the field plate. A first conductive contact has opposing outermost sidewalls intersecting a first horizontally extending surface of the field plate between the gate electrode and the drain region.

公开(公告)号：US11114543B2

公开(公告)日：2021-09-07

申请号：US15460582

申请日：2017-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hong Chang ,  Chih-Yuan Chan ,  Shen-Ping Wang ,  Chung-Cheng Chen ,  Chien-Li Kuo ,  Po-Tao Chu

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/778 ,  H01L21/768 ,  H01L21/74 ,  H01L29/423 ,  H01L23/31 ,  H01L23/532 ,  H01L23/522 ,  H01L29/20

Abstract: A group III-V device structure is provided. The group III-V device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The group III-V device structure also includes a gate structure formed over the active layer and a source electrode and a drain electrode formed over the active layer. The source electrode and the drain electrode are formed on opposite sides of the gate structure. The group III-V device structure further includes a through via structure formed through the channel layer, the active layer and a portion of the substrate, and the through via structure is electrically connected to the source electrode or the drain electrode.

公开(公告)号：US10804231B2

公开(公告)日：2020-10-13

申请号：US16419280

申请日：2019-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/50 ,  H01L23/29

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.