公开(公告)号：US20210328005A1

公开(公告)日：2021-10-21

申请号：US17305276

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku SHEN ,  Ming-Hong KAO ,  Hui-Chi CHEN ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC: H01L49/02

Abstract: A metal-insulator-metal (MIM) capacitor structure includes a bottom electrode, a first oxide layer adjacent the bottom electrode, and a first high-k dielectric layer over the bottom electrode and the first oxide layer. A middle electrode is over the first high-k dielectric layer and a second oxide layer is adjacent the middle electrode. A second high-k dielectric layer may be over the middle electrode and the second oxide layer, a top electrode may be over the second high-k dielectric layer.

公开(公告)号：US20170186849A1

公开(公告)日：2017-06-29

申请号：US15180907

申请日：2016-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hui-Chi CHEN ,  Hsiang-ku SHEN ,  Jeng-Ya David YEH

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/76897 ,  H01L21/76829 ,  H01L29/6656 ,  H01L29/78

Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a π-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.

公开(公告)号：US20210118829A1

公开(公告)日：2021-04-22

申请号：US16655998

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan HUANG ,  Mao-Nan WANG ,  Hui-Chi CHEN ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC: H01L23/00

Abstract: A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first dielectric layer over the semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a second dielectric layer over the first conductive layer and the first dielectric layer. The chip structure includes a first conductive via passing through the second dielectric layer, the first conductive layer, and the first dielectric layer and electrically connected to the first conductive layer. The chip structure includes a second conductive via passing through the second dielectric layer and the first dielectric layer. The chip structure includes a first conductive pad over and in direct contact with the first conductive via. The chip structure includes a second conductive pad over and in direct contact with the second conductive via.

公开(公告)号：US20210118782A1

公开(公告)日：2021-04-22

申请号：US16656879

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan HUANG ,  Hsiang-Ku SHEN ,  Hui-Chi CHEN ,  Tien-I BAO ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC: H01L23/495 ,  H01L23/522 ,  H01L23/48

Abstract: A package structure and method for forming the same are provided. The package structure includes a conductive layer formed over a first substrate, and a dielectric layer formed over the conductive layer. The package structure includes a metal-insulator-metal (MIM) capacitor embedded in the dielectric layer, and a shielding layer formed over the MIM capacitor. The shielding layer is insulated from the MIM capacitor by the dielectric layer. The package structure also includes a first through via formed through the MIM capacitor, and the first through via is connected to the conductive layer, and the first through via is insulated from the shielding layer.

公开(公告)号：US20200235225A1

公开(公告)日：2020-07-23

申请号：US16841727

申请日：2020-04-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-De CHIOU ,  Hui-Chi CHEN ,  Jeng-Ya YEH

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238

Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

公开(公告)号：US20200035780A1

公开(公告)日：2020-01-30

申请号：US16593078

申请日：2019-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan HUANG ,  Chih-Yang PAI ,  Yuan-Yang HSIAO ,  Tsung-Chieh HSIAO ,  Hui-Chi CHEN ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC: H01L49/02 ,  H01L23/64 ,  H01G4/10 ,  H01G4/012

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a first dielectric layer formed on the first spacers, and a second electrode layer formed on the first dielectric layer. The second electrode layer extends from the capacitor region to the non-capacitor region, and the second electrode layer extends beyond an outer sidewall of the first spacer.

公开(公告)号：US20190109211A1

公开(公告)日：2019-04-11

申请号：US16195102

申请日：2018-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-De CHIOU ,  Hui-Chi CHEN ,  Jeng-Ya YEH

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

公开(公告)号：US20180337254A1

公开(公告)日：2018-11-22

申请号：US16049545

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-De CHIOU ,  Hui-Chi CHEN ,  Jeng-Ya YEH

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823842 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

公开(公告)号：US20210020633A1

公开(公告)日：2021-01-21

申请号：US17063243

申请日：2020-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiang-Ku SHEN ,  Chih Wei LU ,  Hui-Chi CHEN ,  Jeng-Ya David YEH

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L21/768

Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.

公开(公告)号：US20190131385A1

公开(公告)日：2019-05-02

申请号：US15794139

申请日：2017-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan HUANG ,  Chih-Yang PAI ,  Yuan-Yang HSIAO ,  Tsung-Chieh HSIAO ,  Hui-Chi CHEN ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC: H01L49/02 ,  H01G4/012 ,  H01G4/10 ,  H01L23/64

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, a bottom electrode layer, a first dielectric layer, a top electrode layer and first dielectric spacers. The bottom electrode layer is positioned over the substrate. The first dielectric layer is positioned over the bottom electrode layer. The top electrode layer is positioned over the first dielectric layer. The first dielectric spacers are positioned on opposite sidewalls of the bottom electrode layer. The first dielectric layer has a first dielectric constant. The first dielectric spacers have a second dielectric constant that is lower than the first dielectric constant.