公开(公告)号：US20210118782A1

公开(公告)日：2021-04-22

申请号：US16656879

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan HUANG ,  Hsiang-Ku SHEN ,  Hui-Chi CHEN ,  Tien-I BAO ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC: H01L23/495 ,  H01L23/522 ,  H01L23/48

Abstract: A package structure and method for forming the same are provided. The package structure includes a conductive layer formed over a first substrate, and a dielectric layer formed over the conductive layer. The package structure includes a metal-insulator-metal (MIM) capacitor embedded in the dielectric layer, and a shielding layer formed over the MIM capacitor. The shielding layer is insulated from the MIM capacitor by the dielectric layer. The package structure also includes a first through via formed through the MIM capacitor, and the first through via is connected to the conductive layer, and the first through via is insulated from the shielding layer.

公开(公告)号：US20160240536A1

公开(公告)日：2016-08-18

申请号：US14621814

申请日：2015-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Kai-Hsuan LEE ,  Cheng-Yu YANG ,  Hsiang-Ku SHEN ,  Han-Ting TSAI ,  Yimin HUANG

IPC: H01L27/092 ,  H01L21/266 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/207 ,  H01L29/36

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/161 ,  H01L29/267 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack and a second gate stack over the semiconductor substrate. The semiconductor device structure also includes a first doped structure over the semiconductor substrate and adjacent to the first gate stack. The first doped structure includes a III-V compound semiconductor material and a dopant. The semiconductor device structure further includes a second doped structure over the semiconductor substrate and adjacent to the second gate stack. The second doped structure includes the III-V compound semiconductor material and the dopant. One of the first doped structure and the second doped structure is an n-type semiconductor structure, and the other one of the first doped structure and the second doped structure is a p-type semiconductor structure.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底和半导体衬底上的第一栅极堆叠和第二栅极堆叠。 半导体器件结构还包括在半导体衬底上并与第一栅极叠层相邻的第一掺杂结构。 第一掺杂结构包括III-V族化合物半导体材料和掺杂剂。 半导体器件结构还包括在半导体衬底上并与第二栅极堆叠相邻的第二掺杂结构。 第二掺杂结构包括III-V族化合物半导体材料和掺杂剂。 第一掺杂结构和第二掺杂结构之一是n型半导体结构，第一掺杂结构和第二掺杂结构中的另一个是p型半导体结构。

公开(公告)号：US20190131421A1

公开(公告)日：2019-05-02

申请号：US15797973

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku SHEN ,  Jin-Mu YIN ,  Tsung-Chieh HSIAO ,  Chia-Lin CHUANG ,  Li-Zhen YU ,  Dian-Hau CHEN ,  Shih-Wei WANG ,  De-Wei YU ,  Chien-Hao CHEN ,  Bo-Cyuan LU ,  Jr-Hung LI ,  Chi-On CHUI ,  Min-Hsiu HUNG ,  Huang-Yi HUANG ,  Chun-Cheng CHOU ,  Ying-Liang CHUANG ,  Yen-Chun HUANG ,  Chih-Tang PENG ,  Cheng-Po CHAU ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

公开(公告)号：US20240386932A1

公开(公告)日：2024-11-21

申请号：US18784872

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan HUANG ,  Yen-Ming CHEN ,  Liang-Wei WANG ,  Dian-Hau CHEN ,  Hsiang-Ku SHEN

IPC: G11C11/16 ,  H01L23/522 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor structure includes a third metal layer immediately above a second metal layer that is over a first metal layer. The second metal layer includes magnetic tunneling junction (MTJ) devices in a memory region and a first conductive feature in a logic region. Each MTJ device includes a bottom electrode and an MTJ stack over the bottom electrode. The third metal layer includes a first via electrically connecting to the first conductive feature, and a slot via over and electrically connecting to the MTJ stack of the MTJ devices. The slot via occupies space extending continuously and laterally from a first one to a last one of the MTJ devices. The first via is as thin as or thinner than the slot via. The third metal layer further includes second and third conductive features electrically connecting to the first via and the slot via, respectively.

公开(公告)号：US20210328005A1

公开(公告)日：2021-10-21

申请号：US17305276

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku SHEN ,  Ming-Hong KAO ,  Hui-Chi CHEN ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC: H01L49/02

Abstract: A metal-insulator-metal (MIM) capacitor structure includes a bottom electrode, a first oxide layer adjacent the bottom electrode, and a first high-k dielectric layer over the bottom electrode and the first oxide layer. A middle electrode is over the first high-k dielectric layer and a second oxide layer is adjacent the middle electrode. A second high-k dielectric layer may be over the middle electrode and the second oxide layer, a top electrode may be over the second high-k dielectric layer.

公开(公告)号：US20180138176A1

公开(公告)日：2018-05-17

申请号：US15870649

申请日：2018-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiang-Ku SHEN ,  Chih Wei LU ,  Janet CHEN ,  Jeng-Ya David YEH

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51

Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.

公开(公告)号：US20170256568A1

公开(公告)日：2017-09-07

申请号：US15061621

申请日：2016-03-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiang-Ku SHEN ,  Yu-Lien HUANG ,  Wilson HUANG ,  Janet CHEN ,  Jeng-Ya David YEH

IPC: H01L27/12 ,  H01L29/49 ,  H01L29/417 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/845 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/66628

Abstract: A semiconductor device includes a first gate structure disposed on a substrate. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode and first sidewall spacers disposed on both side faces of the first gate electrode and the first cap insulating layer. The semiconductor device further includes a first protective layer formed over the first cap insulating layer and at least one of the first sidewall spacers. The first protective layer includes at least one selected from the group consisting of AlON, AlN and amorphous silicon.

公开(公告)号：US20210020633A1

公开(公告)日：2021-01-21

申请号：US17063243

申请日：2020-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiang-Ku SHEN ,  Chih Wei LU ,  Hui-Chi CHEN ,  Jeng-Ya David YEH

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L21/768

Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.

公开(公告)号：US20180337092A1

公开(公告)日：2018-11-22

申请号：US16049305

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hui-Chi CHEN ,  Hsiang-Ku SHEN ,  Jeng-Ya David YEH

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a π-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.

公开(公告)号：US20170317076A1

公开(公告)日：2017-11-02

申请号：US15141476

申请日：2016-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiang-Ku SHEN ,  Chih Wei LU ,  Janet CHEN ,  Jeng-Ya David YEH

IPC: H01L27/088 ,  H01L21/02 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66636

Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.