公开(公告)号：US20210118829A1

公开(公告)日：2021-04-22

申请号：US16655998

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan HUANG ,  Mao-Nan WANG ,  Hui-Chi CHEN ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC: H01L23/00

Abstract: A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first dielectric layer over the semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a second dielectric layer over the first conductive layer and the first dielectric layer. The chip structure includes a first conductive via passing through the second dielectric layer, the first conductive layer, and the first dielectric layer and electrically connected to the first conductive layer. The chip structure includes a second conductive via passing through the second dielectric layer and the first dielectric layer. The chip structure includes a first conductive pad over and in direct contact with the first conductive via. The chip structure includes a second conductive pad over and in direct contact with the second conductive via.

公开(公告)号：US20210118782A1

公开(公告)日：2021-04-22

申请号：US16656879

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan HUANG ,  Hsiang-Ku SHEN ,  Hui-Chi CHEN ,  Tien-I BAO ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC: H01L23/495 ,  H01L23/522 ,  H01L23/48

Abstract: A package structure and method for forming the same are provided. The package structure includes a conductive layer formed over a first substrate, and a dielectric layer formed over the conductive layer. The package structure includes a metal-insulator-metal (MIM) capacitor embedded in the dielectric layer, and a shielding layer formed over the MIM capacitor. The shielding layer is insulated from the MIM capacitor by the dielectric layer. The package structure also includes a first through via formed through the MIM capacitor, and the first through via is connected to the conductive layer, and the first through via is insulated from the shielding layer.

公开(公告)号：US20180076141A1

公开(公告)日：2018-03-15

申请号：US15816843

申请日：2017-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey WU ,  Dian-Hau CHEN ,  Jye-Yen CHENG ,  Sheng-Hsuan WEI ,  Li-Yu LEE ,  TaiYang WU

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/033

CPC classification number: H01L23/5329 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

公开(公告)号：US20240386932A1

公开(公告)日：2024-11-21

申请号：US18784872

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan HUANG ,  Yen-Ming CHEN ,  Liang-Wei WANG ,  Dian-Hau CHEN ,  Hsiang-Ku SHEN

IPC: G11C11/16 ,  H01L23/522 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor structure includes a third metal layer immediately above a second metal layer that is over a first metal layer. The second metal layer includes magnetic tunneling junction (MTJ) devices in a memory region and a first conductive feature in a logic region. Each MTJ device includes a bottom electrode and an MTJ stack over the bottom electrode. The third metal layer includes a first via electrically connecting to the first conductive feature, and a slot via over and electrically connecting to the MTJ stack of the MTJ devices. The slot via occupies space extending continuously and laterally from a first one to a last one of the MTJ devices. The first via is as thin as or thinner than the slot via. The third metal layer further includes second and third conductive features electrically connecting to the first via and the slot via, respectively.

公开(公告)号：US20210143101A1

公开(公告)日：2021-05-13

申请号：US17135791

申请日：2020-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey WU ,  Dian-Hau CHEN ,  Jye-Yen CHENG ,  Sheng-Hsuan WEI ,  Li-Yu LEE ,  TaiYang WU

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

公开(公告)号：US20200035780A1

公开(公告)日：2020-01-30

申请号：US16593078

申请日：2019-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan HUANG ,  Chih-Yang PAI ,  Yuan-Yang HSIAO ,  Tsung-Chieh HSIAO ,  Hui-Chi CHEN ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC: H01L49/02 ,  H01L23/64 ,  H01G4/10 ,  H01G4/012

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a first dielectric layer formed on the first spacers, and a second electrode layer formed on the first dielectric layer. The second electrode layer extends from the capacitor region to the non-capacitor region, and the second electrode layer extends beyond an outer sidewall of the first spacer.

公开(公告)号：US20190157204A1

公开(公告)日：2019-05-23

申请号：US16224031

申请日：2018-12-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey WU ,  Dian-Hau CHEN ,  Jye-Yen CHENG ,  Sheng-Hsuan WEI ,  Li-Yu LEE ,  TaiYang WU

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L21/768

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

公开(公告)号：US20190131421A1

公开(公告)日：2019-05-02

申请号：US15797973

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku SHEN ,  Jin-Mu YIN ,  Tsung-Chieh HSIAO ,  Chia-Lin CHUANG ,  Li-Zhen YU ,  Dian-Hau CHEN ,  Shih-Wei WANG ,  De-Wei YU ,  Chien-Hao CHEN ,  Bo-Cyuan LU ,  Jr-Hung LI ,  Chi-On CHUI ,  Min-Hsiu HUNG ,  Huang-Yi HUANG ,  Chun-Cheng CHOU ,  Ying-Liang CHUANG ,  Yen-Chun HUANG ,  Chih-Tang PENG ,  Cheng-Po CHAU ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

公开(公告)号：US20190131385A1

公开(公告)日：2019-05-02

申请号：US15794139

申请日：2017-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan HUANG ,  Chih-Yang PAI ,  Yuan-Yang HSIAO ,  Tsung-Chieh HSIAO ,  Hui-Chi CHEN ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC: H01L49/02 ,  H01G4/012 ,  H01G4/10 ,  H01L23/64

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, a bottom electrode layer, a first dielectric layer, a top electrode layer and first dielectric spacers. The bottom electrode layer is positioned over the substrate. The first dielectric layer is positioned over the bottom electrode layer. The top electrode layer is positioned over the first dielectric layer. The first dielectric spacers are positioned on opposite sidewalls of the bottom electrode layer. The first dielectric layer has a first dielectric constant. The first dielectric spacers have a second dielectric constant that is lower than the first dielectric constant.

公开(公告)号：US20170221827A1

公开(公告)日：2017-08-03

申请号：US15484344

申请日：2017-04-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey WU ,  Dian-Hau CHEN ,  Jye-Yen CHENG ,  Sheng-Hsuan WEI ,  Li-Yu LEE ,  TaiYang WU

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/528 ,  H01L21/027

CPC classification number: H01L23/5329 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.