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    Integrated thermoelectric devices in Fin FET technology
    2.
    发明授权
    Integrated thermoelectric devices in Fin FET technology 有权

    公开(公告)号：US11424399B2

    公开(公告)日：2022-08-23

    申请号：US14793586

    申请日：2015-07-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jhong-Sheng Wang ,  Jiaw-Ren Shih ,  Hsiao-Hsuan Hsu

    IPC: H01L35/00 ,  H01L35/32 ,  H01L35/34 ,  H01L35/30 ,  H01L27/16 ,  H01L29/78

    Abstract: Operations for integrating thermoelectric devices in Fin FET technology may be implemented in a semiconductor device having a thermoelectric device. The thermoelectric device includes a substrate and a fin structure disposed on the substrate. The thermoelectric device includes a first connecting layer and a second connecting layer disposed on opposing ends of the fin structure. The thermoelectric device includes a first thermal conductive structure thermally and a second thermal conductive structure thermally coupled to the opposing ends of the fin structure. The fin structure may be configured to transfer heat from one of the first thermal conductive structure or the second thermal conductive structure to the other thermal conductive structure based on a direction of current flow through the fin structure. In this regard, the current flow may be adjusted by a power circuit electrically coupled to the thermoelectric device.

    Method for writing to magnetic random access memory
    6.
    发明授权
    Method for writing to magnetic random access memory 有权

    公开(公告)号：US10685693B2

    公开(公告)日：2020-06-16

    申请号：US16377036

    申请日：2019-04-05

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ji-Feng Ying ,  Jhong-Sheng Wang ,  Baohua Niu

    IPC: G11C11/00 ,  G11C11/16

    Abstract: A method of manufacturing an array of magnetic random access memory cells includes writing to a magnetic random access memory cell. The writing to a memory cell includes determining an optimum write current for the array of memory cells, and applying the optimum write current to a first memory cell in the array. A first read current is applied to the first memory cell to determine whether a magnetic orientation of the first memory cell has changed in response to applying the optimum write current. A second write current is applied to the first memory cell when the magnetic orientation of the first memory cell has not changed. The second write current is different from the optimum write current. A second read current is applied to the first memory cell to determine whether the magnetic orientation of the first memory cell changed in response to applying the second write current.

    Transistor and method of manufacturing the same
    7.
    发明授权
    Transistor and method of manufacturing the same 有权
    晶体管及其制造方法

    公开(公告)号：US09373712B2

    公开(公告)日：2016-06-21

    申请号：US14500626

    申请日：2014-09-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jhong-Sheng Wang ,  Jiaw-Ren Shih

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4966 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

    Abstract: A transistor includes source region and drain regions, a channel region, a drift region, a gate, a dummy gate, a gate dielectric layer and an interconnection line. The source and drain regions of a first conductivity type are in a substrate. The channel region of a second conductivity type is in the substrate and surrounds the source region. The drift region of the first conductivity type is beneath the drain region and extends toward the channel region. The gate is over the substrate and overlapped with the channel region and the drift region. The dummy gate is over the drift region and laterally adjacent to the gate. The gate dielectric layer is between the gate and the substrate and between the dummy gate and the drift region. The interconnection line is electrically connected to the dummy gate and configured to provide a voltage potential thereto.

    Abstract translation: 晶体管包括源极区和漏极区，沟道区，漂移区，栅极，虚拟栅极，栅极介电层和互连线。 第一导电类型的源区和漏区在衬底中。 第二导电类型的沟道区位于衬底中并围绕源极区。 第一导电类型的漂移区域在漏极区域下方并且朝向沟道区域延伸。 栅极在衬底上方并与沟道区域和漂移区域重叠。 虚拟栅极位于漂移区之上，并且横向邻近栅极。 栅极电介质层位于栅极和衬底之间以及虚拟栅极和漂移区域之间。 互连线电连接到虚拟栅极并且被配置为向其提供电压电位。

    Method for writing to magnetic random access memory
    8.
    发明授权
    Method for writing to magnetic random access memory 有权

    公开(公告)号：US11238911B2

    公开(公告)日：2022-02-01

    申请号：US16902134

    申请日：2020-06-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ji-Feng Ying ,  Jhong-Sheng Wang ,  Baohua Niu

    IPC: G11C11/00 ,  G11C11/16

    Abstract: A method of manufacturing an array of magnetic random access memory cells includes writing to a magnetic random access memory cell. The writing to a memory cell includes determining an optimum write current for the array of memory cells, and applying the optimum write current to a first memory cell in the array. A first read current is applied to the first memory cell to determine whether a magnetic orientation of the first memory cell has changed in response to applying the optimum write current. A second write current is applied to the first memory cell when the magnetic orientation of the first memory cell has not changed. The second write current is different from the optimum write current. A second read current is applied to the first memory cell to determine whether the magnetic orientation of the first memory cell changed in response to applying the second write current.

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