公开(公告)号：US11004901B2

公开(公告)日：2021-05-11

申请号：US16743992

申请日：2020-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ji-Feng Ying ,  Duen-Huei Hou

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  B82Y25/00

Abstract: A semiconductor device includes a magnetic random access memory (MRAM) cell. The MRAM cell includes a first magnetic layer disposed over a substrate, a first non-magnetic material layer made of a non-magnetic material and disposed over the first magnetic layer, a second magnetic layer disposed over the first non-magnetic material layer, and a second non-magnetic material layer disposed over the second magnetic layer. The second magnetic layer includes a plurality of magnetic material pieces separated from each other.

公开(公告)号：US10727401B2

公开(公告)日：2020-07-28

申请号：US15906901

申请日：2018-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Baohua Niu ,  Ji-Feng Ying

IPC: H01L43/10 ,  G11C11/16 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L21/62

Abstract: A memory cell of a magnetic random access memory includes multiple layers disposed between a first metal layer and a second metal layer. At least one of the multiple layers include one selected from the group consisting of an iridium layer, a bilayer structure of an iridium layer and an iridium oxide layer, an iridium-titanium nitride layer, a bilayer structure of an iridium layer and a tantalum layer, and a binary alloy layer of iridium and tantalum.

公开(公告)号：US10672832B2

公开(公告)日：2020-06-02

申请号：US15875140

申请日：2018-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ji-Feng Ying ,  Baohua Niu

IPC: H01L27/22 ,  G11C11/16 ,  H01F10/14 ,  H01F10/16 ,  H01F10/32 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic detection circuit for a magnetic random access memory (MRAM) is provided. The magnetic detection circuit includes a sensing array including a plurality of sensing cells and a controller. Each of the sensing cells includes a first magnetic tunnel junction (MTJ) device. The controller is configured to access the first MRAM cells to detect the external magnetic field strength of the MRAM. The controller determines whether to stop the write operation of a plurality of memory cells of the MRAM according to the external magnetic field strength of the MRAM, and each of the memory cells includes a second MTJ device. The first MTJ device is smaller than the second MTJ device.

公开(公告)号：US10510410B2

公开(公告)日：2019-12-17

申请号：US15905699

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ji-Feng Ying ,  Baohua Niu ,  Jhong-Sheng Wang

IPC: G11C13/00

Abstract: In the disclosure, a non-volatile memory device includes a resistive memory cell and a write and read circuit. The write and read circuit is coupled to the resistive memory cell and configured to combine a perturbation AC signal with a first writing signal, so as to generate a second writing signal. Then, the write and read circuit applies the second writing signal to the resistive memory cell to program the resistive memory cell. The combination of the oscillation signal and the first writing signal (constant DC signal) and AC signal would penetrate the shielding effect of the insulating layer and free the stuck charges.

公开(公告)号：US10403385B2

公开(公告)日：2019-09-03

申请号：US15993709

申请日：2018-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Baohua Niu ,  Ji-Feng Ying

IPC: G11C29/08 ,  G11C29/12 ,  G11C11/16 ,  G11C13/00 ,  G11C29/44 ,  G11C29/50 ,  G11C29/02 ,  G11C29/56 ,  G11C29/04

Abstract: A memory test system is disclosed that includes a memory integrated circuit (IC) and a memory functional tester. The memory IC includes a plurality of memory banks, where each memory bank includes a plurality of memory cells. The memory functional tester includes an adjustable voltage generator circuit, a read current measurement circuit, and a controller. The memory functional tester performs a write/read functional test on the memory bank over a number of write control voltages to determine a preferred write control voltage, where the preferred write control voltage is designated for use during subsequent write operations to the memory bank during an operational mode.

公开(公告)号：US11762046B2

公开(公告)日：2023-09-19

申请号：US17001486

申请日：2020-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Baohua Niu ,  Ji-Feng Ying

IPC: G01R33/26 ,  G01R33/12 ,  G01Q60/08 ,  G01Q60/52 ,  G01Q70/14 ,  G01Q30/02 ,  G01R33/32 ,  G01R33/032 ,  G01Q60/38

CPC classification number: G01R33/26 ,  G01Q30/025 ,  G01Q60/08 ,  G01Q60/52 ,  G01Q70/14 ,  G01R33/032 ,  G01R33/12 ,  G01R33/323 ,  G01Q60/38

Abstract: An apparatus for measuring a magnetic field strength is provided. The apparatus includes a stage on which a sample to be measured is placed, a cantilever having a tip, an optical system having a light source and a light receiver, and a microwave power source. The tip is a diamond tip having a nitrogen vacancy defect. The optical system is configured such that excitation light from the light source is focused at the diamond tip. The cantilever is configured as a coaxial microwave antenna through which microwaves from the microwave power source are supplied to the diamond tip.

公开(公告)号：US11238911B2

公开(公告)日：2022-02-01

申请号：US16902134

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ji-Feng Ying ,  Jhong-Sheng Wang ,  Baohua Niu

IPC: G11C11/00 ,  G11C11/16

Abstract: A method of manufacturing an array of magnetic random access memory cells includes writing to a magnetic random access memory cell. The writing to a memory cell includes determining an optimum write current for the array of memory cells, and applying the optimum write current to a first memory cell in the array. A first read current is applied to the first memory cell to determine whether a magnetic orientation of the first memory cell has changed in response to applying the optimum write current. A second write current is applied to the first memory cell when the magnetic orientation of the first memory cell has not changed. The second write current is different from the optimum write current. A second read current is applied to the first memory cell to determine whether the magnetic orientation of the first memory cell changed in response to applying the second write current.

公开(公告)号：US11244714B2

公开(公告)日：2022-02-08

申请号：US17170633

申请日：2021-02-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ji-Feng Ying ,  Jhong-Sheng Wang ,  Duen-Huei Hou

IPC: G11C11/00 ,  G11C11/16 ,  H01F10/32 ,  H01L21/66 ,  H01L43/02 ,  H01L43/12

Abstract: A method of writing to a magnetic random access memory cell includes applying an alternating current signal to the magnetic random access memory cell having a first magnetic orientation, and applying a direct current pulse to the magnetic random access memory cell to change the magnetic orientation of the magnetic random access memory cell from the first magnetic orientation to a second magnetic orientation. The first magnetic orientation and the second magnetic orientation are different.

公开(公告)号：US20210036055A1

公开(公告)日：2021-02-04

申请号：US16739016

申请日：2020-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ji-Feng Ying ,  Jhong-Sheng Wang ,  Tsann Lin

IPC: H01L27/22 ,  H01L23/528 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01L23/522 ,  H01F10/32 ,  H01F41/32

Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.

公开(公告)号：US20200098408A1

公开(公告)日：2020-03-26

申请号：US16503692

申请日：2019-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsann Lin ,  Ji-Feng Ying ,  Chih-Chung Lai

IPC: G11C11/16 ,  H01L43/10 ,  H01F10/32 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01F41/34

Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.