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    Fin Isolation Regions With Improved Depth Distribution and Methods Forming the Same
    1.
    发明公开
    Fin Isolation Regions With Improved Depth Distribution and Methods Forming the Same 审中-公开

    公开(公告)号：US20240312843A1

    公开(公告)日：2024-09-19

    申请号：US18184024

    申请日：2023-03-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tzu-Ging Lin ,  Yi-Chun Chen ,  Jih-Jse Lin

    IPC: H01L21/8234 ,  H01L27/088

    CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L27/0886

    Abstract: A method includes forming a gate stack on a semiconductor region, wherein the semiconductor region is over a bulk semiconductor substrate. The gate stack is etched to form a first trench, wherein a plurality of protruding semiconductor fins are revealed to the first trench. The plurality of protruding semiconductor fins are etched to form a plurality of second trenches extending into the bulk semiconductor substrate. The plurality of second trenches are underlying and joined to the first trench. The plurality of second trenches include a first outmost trench having a first depth, a second outmost trench, and an inner trench between the first outmost trench and the second outmost trench. The inner trench has a second depth equal to or smaller than the first depth. A fin isolation region is formed to fill the first trench and the plurality of second trenches.

    Methods of forming FinFET devices
    2.
    发明授权
    Methods of forming FinFET devices 有权

    公开(公告)号：US11152249B2

    公开(公告)日：2021-10-19

    申请号：US16874677

    申请日：2020-05-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jih-Jse Lin ,  Ryan Chia-Jen Chen ,  Fang-Cheng Chen ,  Ming-Ching Chang

    IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/764 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/311 ,  H01L29/165

    Abstract: A method of forming a FinFET device includes following steps. A substrate is provided with a plurality of fins thereon, an isolation layer thereon covering lower portions of the fins, a plurality of dummy strips across the fins, and a dielectric layer aside the dummy strips. The dummy strips is cut to form a trench in the dielectric layer. A first insulating structure is formed in the trench, wherein first and second groups of the dummy strips are beside the first insulating structure. A dummy strip is removed from the first group of the dummy strips to form a first opening that exposes portions of the fins under the dummy strip. The portions of the fins are removed to form a plurality of second openings below the first opening, wherein each second opening has a middle-wide profile. A second insulating structure is formed in the first and second openings.

    METHODS OF FORMING FINFET DEVICES
    7.
    发明申请
    METHODS OF FORMING FINFET DEVICES 审中-公开

    公开(公告)号：US20200312709A1

    公开(公告)日：2020-10-01

    申请号：US16874677

    申请日：2020-05-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jih-Jse Lin ,  Ryan Chia-Jen Chen ,  Fang-Cheng Chen ,  Ming-Ching Chang

    IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/764 ,  H01L27/088 ,  H01L21/3065 ,  H01L29/66

    Abstract: A method of forming a FinFET device includes following steps. A substrate is provided with a plurality of fins thereon, an isolation layer thereon covering lower portions of the fins, a plurality of dummy strips across the fins, and a dielectric layer aside the dummy strips. The dummy strips is cut to form a trench in the dielectric layer. A first insulating structure is formed in the trench, wherein first and second groups of the dummy strips are beside the first insulating structure. A dummy strip is removed from the first group of the dummy strips to form a first opening that exposes portions of the fins under the dummy strip. The portions of the fins are removed to form a plurality of second openings below the first opening, wherein each second opening has a middle-wide profile. A second insulating structure is formed in the first and second openings.

    Multi-zone temperature control for semiconductor wafer
    8.
    发明授权
    Multi-zone temperature control for semiconductor wafer 有权
    半导体晶圆的多区域温度控制

    公开(公告)号：US09023664B2

    公开(公告)日：2015-05-05

    申请号：US13777212

    申请日：2013-02-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo-Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

    IPC: H01L21/00 ,  H01L21/66 ,  H01L21/67

    CPC classification number: H01L22/20 ,  H01L21/67248 ,  H01L21/67253 ,  H01L22/12

    Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.

    Abstract translation: 提供了一种用于控制电路的关键尺寸（CD）的装置和方法。 一种装置包括控制器，用于在第一基板上的蚀刻膜中的电路图案的各个位置处接收CD测量值，以及用于在第二基板上形成膜材料的第二膜的单晶片室。 单个晶片室响应于来自控制器的信号，以基于测量的CD来局部地调整第二胶片的厚度。 一种方法提供了蚀刻第一衬底上的膜的电路图案，测量电路图案的CD，基于所测量的CD调整单晶片室以在第二半导体衬底上形成第二膜。 基于测量的CD来局部地调整第二膜厚度。

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