公开(公告)号：US20220351939A1

公开(公告)日：2022-11-03

申请号：US17245724

申请日：2021-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng CHANG ,  Chan-Lon YANG ,  Perng-Fei YUH

IPC: H01J37/305 ,  H01J37/08

Abstract: The present disclosure relates to an ion beam etching (IBE) system including a plasma chamber configured to provide plasma, a screen grid, an extraction grid, an accelerator grid, and a decelerator grid. The screen grid receives a screen grid voltage to extract ions from the plasma within the plasma chamber to form an ion beam through a hole. The extraction grid receives an extraction grid voltage, where a voltage difference between the screen grid voltage and the extraction grid voltage determines an ion current density of the ion beam. The accelerator grid receives an accelerator grid voltage. A voltage difference between the extraction grid voltage and the accelerator grid voltage determines an ion beam energy for the ion beam. The IBE system can further includes a deflector system having a first deflector plate and a second deflector plate around a hole to control the direction of the ion beam.

公开(公告)号：US20230395685A1

公开(公告)日：2023-12-07

申请号：US18231486

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng CHANG ,  Chan-Lon YANG ,  Perng-Fei YUH

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/78696 ,  H01L29/66545 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/1037 ,  H01L29/0673

Abstract: A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.

公开(公告)号：US20230031722A1

公开(公告)日：2023-02-02

申请号：US17383962

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng CHANG ,  Chan-Lon YANG ,  Perng-Fei YUH

IPC: H01J37/08 ,  H01L21/311 ,  H01J37/32

Abstract: The present disclosure relates to an ion beam etching (IBE) system including a process chamber. The process chamber includes a plasma chamber configured to provide plasma. In addition, the process chamber includes an accelerator grid having multiple accelerator grid elements including a first accelerator grid element and a second accelerator grid element. A first wire is coupled to the first accelerator grid element and configured to supply a first voltage to the first accelerator grid element. A second wire is coupled to the second accelerator grid element and configured to supply a second voltage to the second accelerator grid element, where the second voltage is different from the first voltage. A first ion beam through a first hole is controlled by the first accelerator grid element, and a second ion beam through a second hole is controlled by the second accelerator grid element.

公开(公告)号：US20220384599A1

公开(公告)日：2022-12-01

申请号：US17334541

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng CHANG ,  Chan-Lon YANG ,  Perng-Fei YUH

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.

公开(公告)号：US20220199457A1

公开(公告)日：2022-06-23

申请号：US17694158

申请日：2022-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chansyun David YANG ,  Chan-Lon YANG ,  Keh-Jeng CHANG ,  Perng-Fei YUH

IPC: H01L21/687 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/311

Abstract: The present disclosure describes methods and systems for radical-activated etching of a metal oxide. The system includes a chamber, a wafer holder configured to hold a wafer with a metal oxide disposed thereon, a first gas line fluidly connected to the chamber and configured to deliver a gas to the chamber, a plasma generator configured to generate a plasma from the gas, a grid system between the plasma generator and the wafer holder and configured to increase a kinetic energy of ions from the plasma, a neutralizer between the grid system and the wafer holder and configured to generate electrons and neutralize the ions to generate radicals, and a second gas line fluidly connected to the chamber and configured to deliver a precursor across the wafer. The radicals facilitate etching of the metal oxide by the precursor.

公开(公告)号：US20220367627A1

公开(公告)日：2022-11-17

申请号：US17320170

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng CHANG ,  Chan-Lon YANG ,  Perng-Fei YUH

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a stack of nanostructured channel regions disposed on a fin structure, a first gate structure disposed within the stack of nanostructured channel regions, a second gate structure surrounds the first gate structure about a first axis and surrounds the nanostructured channel regions about a second axis different from the first axis, and first and second contact structures disposed on the first and second gate structures, respectively.

公开(公告)号：US20210376226A1

公开(公告)日：2021-12-02

申请号：US16884297

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Perng-Fei YUH ,  Yih WANG

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  G11C5/02

Abstract: Magnetic random access memory (MRAM) cells are provided. An MRAM cell includes a plurality of stacked magnetic tunnel junction (MTJ) devices coupled in serial and a transistor. The transistor having a gate coupled to a word line, a first terminal coupled to a bit line through the stacked MTJ devices, and a second terminal coupled to a source line. The stacked MTJ devices are different sizes.