公开(公告)号：US12230574B2

公开(公告)日：2025-02-18

申请号：US18361560

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gulbagh Singh ,  Kun-Tsang Chuang ,  Po-Jen Wang

IPC: H01L23/535 ,  H01L21/74 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/482 ,  H01L23/485 ,  H01L27/12

Abstract: The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.

公开(公告)号：US11201082B2

公开(公告)日：2021-12-14

申请号：US16686124

申请日：2019-11-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hua Yen ,  Ching-Hung Kao ,  Po-Jen Wang ,  Tsung-Han Tsai

IPC: H01L21/762 ,  H01L29/06 ,  H01L27/12 ,  H01L21/306 ,  H01L21/311 ,  H01L21/764 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/027 ,  H01L21/308 ,  H01L21/3105

Abstract: A method includes forming an isolation region between a plurality of active regions of a semiconductor substrate, forming at least one deep trench extending from the isolation region toward a bottom of the semiconductor substrate, and forming an interlayer dielectric layer over the semiconductor substrate. The interlayer dielectric layer fills in the deep trench to form a deep trench isolation structure and an air void in the deep trench isolation structure.

公开(公告)号：US20210057517A1

公开(公告)日：2021-02-25

申请号：US16549835

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting CHEN ,  Tsung-Han Tsai ,  Kun-Tsang Chuang ,  Po-Jen Wang ,  Ying-Hao Chen ,  Chien-Cheng Chuang

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/3213

Abstract: The present disclosure relates to an apparatus that includes a bottom electrode and a dielectric structure. The dielectric structure includes a first dielectric layer on the bottom electrode and the first dielectric layer has a first thickness. The apparatus also includes a blocking layer on the first dielectric layer and a second dielectric layer on the blocking layer. The second dielectric layer has a second thickness that is less than the first thickness. The apparatus further includes a top electrode over the dielectric structure.

公开(公告)号：US10804389B2

公开(公告)日：2020-10-13

申请号：US15054078

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Ching Wu ,  Po-Jen Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/088 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423

Abstract: A MOS transistor includes a substrate, a first region, a second region, a source region, a drain region, an active gate stack, and a dummy gate stack. The substrate has a first conductivity. The first region having the first conductivity is formed in the substrate. The second region having a second conductivity is formed in the substrate and is adjacent to the first region. The source region with the second conductivity is formed in the first region. The drain region with the second conductivity is formed in the second region. The active gate stack is disposed on the first region. The dummy gate stack is disposed on the second region, and the dummy gate stack is electrically coupled to a variable voltage.

公开(公告)号：US09449976B2

公开(公告)日：2016-09-20

申请号：US14104987

申请日：2013-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Ching Wu ,  Hsiang-Hui Tsai ,  Po-Jen Wang ,  Hung-Che Liao

IPC: H01L29/76 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0928 ,  H01L21/823878 ,  H01L21/823892

Abstract: A novel semiconductor device structure includes a first-conductivity-type semiconductor substrate, an isolated region, a first-conductivity-type MOS region, and a second-conductivity-type MOS region. A first-conductivity-type MOS transistor locates in the first-conductivity-type MOS region with a second-conductivity-type well surrounding, and a first-conductivity-type deep well surrounding the second-conductivity-type well with a second-conductivity-type deep well surrounding. In the second-conductivity-type MOS region, a second-conductivity-type MOS transistor is formed with a first-conductivity-type well surrounding. The first-conductivity-type deep well and the second-conductivity-type deep well are sufficiently reducing the noise and current leakage from other devices or from the semiconductor substrate.

Abstract translation: 一种新颖的半导体器件结构包括第一导电型半导体衬底，隔离区，第一导电型MOS区和第二导电型MOS区。 第一导电型MOS晶体管位于具有第二导电型阱的第一导电型MOS区中，并且围绕第二导电型阱的第一导电型深阱具有第二导电性 型深井环绕。 在第二导电型MOS区中，第二导电型MOS晶体管形成有第一导电型阱。 第一导电型深井和第二导电型深井充分降低了来自其它装置或半导体基板的噪声和电流泄漏。

公开(公告)号：US11682549B2

公开(公告)日：2023-06-20

申请号：US17169499

申请日：2021-02-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-Wen Hsu ,  Ching-Hung Kao ,  Po-Jen Wang ,  Tsung-Han Tsai

IPC: H01L21/02 ,  H01L21/683 ,  H01L21/687 ,  H01L21/67 ,  H01L21/22 ,  H01L27/12

CPC classification number: H01L21/02016 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/67103 ,  H01L21/6831 ,  H01L21/68757 ,  H01L21/68764 ,  H01L21/68785 ,  H01J2237/31701 ,  H01L27/1203

Abstract: A method comprises depositing a mask layer on a front-side surface of a wafer, wherein a portion of the wafer has a first resistivity; with the mask layer in place, performing an ion implantation process on a backside surface of the wafer to implant a resistivity reduction impurity into the wafer through the backside surface of the wafer to lower the first resistivity of the portion of the wafer to a second resistivity; after performing the ion implantation process, removing the mask layer from the front-side surface of the wafer; and forming semiconductor devices on the front-side surface of the wafer.

公开(公告)号：US20210327813A1

公开(公告)日：2021-10-21

申请号：US16849709

申请日：2020-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gulbagh Singh ,  Kun-Tsang Chuang ,  Po-Jen Wang

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/532 ,  H01L21/74 ,  H01L21/768

Abstract: The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.

公开(公告)号：US10916416B2

公开(公告)日：2021-02-09

申请号：US16171950

申请日：2018-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-Wen Hsu ,  Ching-Hung Kao ,  Po-Jen Wang ,  Tsung-Han Tsai

IPC: H01L21/02 ,  H01L21/683 ,  H01L21/687 ,  H01L21/67 ,  H01L21/22 ,  H01L27/12

Abstract: A semiconductor wafer and a semiconductor wafer fabrication method are provided. The wafer includes a supporting substrate, a semiconductor substrate and a contact layer. The supporting substrate has a first surface and a second surface opposite to the first surface. The semiconductor substrate is disposed on the first surface of the supporting substrate, in which the semiconductor substrate is configured to form plural devices. The contact layer is disposed on the second surface of the supporting substrate to contact the supporting substrate, in which the contact layer is configured to contact an electrostatic chuck and has a resistivity of the contact layer smaller than a resistivity of the supporting substrate. In semiconductor wafer fabrication method, at first, a raw wafer is provided. Then, the contact layer is formed by using an implantation operation or a deposition operation.

公开(公告)号：US10483153B2

公开(公告)日：2019-11-19

申请号：US15885524

申请日：2018-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hua Yen ,  Ching-Hung Kao ,  Po-Jen Wang ,  Tsung-Han Tsai

IPC: H01L21/762 ,  H01L29/06 ,  H01L27/12 ,  H01L21/306 ,  H01L21/311 ,  H01L21/764 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/027 ,  H01L21/308 ,  H01L21/3105

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region, a first active component and at least one deep trench isolation structure. The isolation region is in the semiconductor substrate. The first active component is on the semiconductor substrate. The deep trench isolation structure extends from a bottom of the isolation region toward a bottom of the semiconductor substrate. The deep trench isolation structure has at least one air void therein.

公开(公告)号：US20150171087A1

公开(公告)日：2015-06-18

申请号：US14104987

申请日：2013-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Ching WU ,  Hsiang-Hui Tsai ,  Po-Jen Wang ,  Hung-Che Liao

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0928 ,  H01L21/823878 ,  H01L21/823892

Abstract: A novel semiconductor device structure includes a first-conductivity-type semiconductor substrate, an isolated region, a first-conductivity-type MOS region, and a second-conductivity-type MOS region. A first-conductivity-type MOS transistor locates in the first-conductivity-type MOS region with a second-conductivity-type well surrounding, and a first-conductivity-type deep well surrounding the second-conductivity-type well with a second-conductivity-type deep well surrounding. In the second-conductivity-type MOS region, a second-conductivity-type MOS transistor is formed with a first-conductivity-type well surrounding. The first-conductivity-type deep well and the second-conductivity-type deep well are sufficiently reducing the noise and current leakage from other devices or from the semiconductor substrate.

Abstract translation: 一种新颖的半导体器件结构包括第一导电型半导体衬底，隔离区，第一导电型MOS区和第二导电型MOS区。 第一导电型MOS晶体管位于具有第二导电型阱的第一导电型MOS区中，并且围绕第二导电型阱的第一导电型深阱具有第二导电性 型深井环绕。 在第二导电型MOS区中，第二导电型MOS晶体管形成有第一导电型阱。 第一导电型深井和第二导电型深井充分降低了来自其它装置或半导体基板的噪声和电流泄漏。