公开(公告)号：US20190122933A1

公开(公告)日：2019-04-25

申请号：US16222621

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Wei-Ting CHEN

IPC: H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L27/088

Abstract: A method for manufacturing a semiconductor device includes forming first and second fins over a substrate, forming first and second dummy gate structures over the first and second fins, respectively, replacing the first and second dummy gate structures with first and second gate structures, respectively, and after replacing the first and second dummy gate structures, forming an insulating structure between the first and second gate structures.

公开(公告)号：US20160351700A1

公开(公告)日：2016-12-01

申请号：US14725118

申请日：2015-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Che-Cheng CHANG ,  Jui-Ping CHUANG ,  Chen-Hsiang LU ,  Wei-Ting CHEN ,  Yu-Cheng LIU

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底上的翅片结构和覆盖翅片结构的一部分的栅极堆叠。 栅堆叠包括功函数层和栅介质层。 半导体器件结构还包括位于半导体衬底上并与栅堆叠相邻的隔离元件。 隔离元件与功函数层和栅极电介质层直接接触，并且隔离元件的较低宽度大于隔离元件的上部宽度。

公开(公告)号：US20160372566A1

公开(公告)日：2016-12-22

申请号：US15257567

申请日：2016-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Chen-Hsiang LU ,  Wei-Ting CHEN ,  Yu-Cheng LIU

IPC: H01L29/66 ,  H01L23/522 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L29/6653 ,  H01L21/28008 ,  H01L21/28247 ,  H01L21/31116 ,  H01L23/5226 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: One or more formation methods of a semiconductor device structure are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements. The method further includes partially removing the spacer elements such that an upper portion of the recess becomes wider. In addition, the method includes forming a metal gate stack in the recess and forming a protection element over the metal gate stack to fill the recess.

Abstract translation: 提供半导体器件结构的一种或多种形成方法。 该方法包括在半导体衬底上形成虚拟栅极堆叠并在虚拟栅极叠层的侧壁上形成间隔元件。 该方法还包括去除虚拟栅极堆叠以在间隔元件之间形成凹陷。 该方法还包括部分去除间隔元件，使得凹部的上部变宽。 此外，该方法包括在凹槽中形成金属栅极叠层，并在金属栅极叠层上形成保护元件以填充凹槽。

公开(公告)号：US20160276272A1

公开(公告)日：2016-09-22

申请号：US14659170

申请日：2015-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Wei-Ting CHEN ,  Che-Cheng CHANG ,  Chen-Hsiang LU ,  Yu-Cheng LIU

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76804 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76832 ,  H01L23/53295

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure includes a second dielectric layer over the first dielectric layer. The first dielectric layer and the second dielectric layer are made of different materials. The semiconductor device structure includes a conductive via structure passing through the first dielectric layer and penetrating into the second dielectric layer. The conductive via structure has a first portion and a second portion. The first portion and the second portion are in the first dielectric layer and the second dielectric layer respectively. The first portion has a first end portion facing the substrate. A first width of the first end portion is greater than a second width of the second portion.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括衬底和衬底上的第一介电层。 半导体器件结构包括在第一介电层上的第二介电层。 第一电介质层和第二电介质层由不同的材料制成。 半导体器件结构包括穿过第一介电层并穿透到第二介电层中的导电通孔结构。 导电通孔结构具有第一部分和第二部分。 第一部分和第二部分分别在第一介电层和第二介电层中。 第一部分具有面向衬底的第一端部。 第一端部的第一宽度大于第二部分的第二宽度。

公开(公告)号：US20160351669A1

公开(公告)日：2016-12-01

申请号：US14725002

申请日：2015-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yin SHIAO ,  Che-Cheng CHANG ,  Tai-Shin CHENG ,  Wei-Ting CHEN

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/76816 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76877 ,  H01L23/485 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming the semiconductor device structure is provided. The method includes forming a first metal layer over a substrate and forming a dielectric layer over the first metal layer. The method includes forming an antireflection layer over the dielectric layer, forming a hard mask layer over the antireflection layer and forming a patterned photoresist layer over the hard mask layer. The method includes etching a portion of the antireflection layer by performing a first etching process and etching through the antireflection layer and etching a portion of the dielectric layer by performing a second etching process. The method includes etching through the dielectric layer by performing a third etching process to form a via portion on the first metal layer. The via portion includes a first sidewall and a second sidewall, and the slope of the first sidewall is different from that of the second sidewall.

Abstract translation: 提供了一种形成半导体器件结构的方法。 该方法包括在衬底上形成第一金属层，并在第一金属层上形成电介质层。 该方法包括在电介质层上形成抗反射层，在抗反射层上形成硬掩模层，并在硬掩模层上形成图案化的光致抗蚀剂层。 该方法包括通过执行第一蚀刻工艺和蚀刻穿过抗反射层并通过执行第二蚀刻工艺蚀刻介电层的一部分来蚀刻抗反射层的一部分。 该方法包括通过执行第三蚀刻工艺来蚀刻通过介电层，以在第一金属层上形成通孔部分。 通孔部分包括第一侧壁和第二侧壁，并且第一侧壁的斜面与第二侧壁的斜面不同。

公开(公告)号：US20160351568A1

公开(公告)日：2016-12-01

申请号：US14725555

申请日：2015-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Jui-Ping CHUANG ,  Chen-Hsiang LU ,  Wei-Ting CHEN ,  Yu-Cheng LIU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66795 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括在半导体衬底上的鳍结构。 半导体器件结构还包括覆盖鳍结构的一部分的栅极堆叠，并且栅极堆叠包括功函数层和在功函数层上的金属填充。 半导体器件结构还包括在半导体衬底上并且邻近栅堆叠的隔离元件。 隔离元件与功函数层和金属填充物直接接触。

公开(公告)号：US20210057517A1

公开(公告)日：2021-02-25

申请号：US16549835

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting CHEN ,  Tsung-Han Tsai ,  Kun-Tsang Chuang ,  Po-Jen Wang ,  Ying-Hao Chen ,  Chien-Cheng Chuang

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/3213

Abstract: The present disclosure relates to an apparatus that includes a bottom electrode and a dielectric structure. The dielectric structure includes a first dielectric layer on the bottom electrode and the first dielectric layer has a first thickness. The apparatus also includes a blocking layer on the first dielectric layer and a second dielectric layer on the blocking layer. The second dielectric layer has a second thickness that is less than the first thickness. The apparatus further includes a top electrode over the dielectric structure.

公开(公告)号：US20180033698A1

公开(公告)日：2018-02-01

申请号：US15727626

申请日：2017-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Wei-Ting CHEN

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

公开(公告)号：US20160276340A1

公开(公告)日：2016-09-22

申请号：US14754627

申请日：2015-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Wei-Ting CHEN

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

Abstract translation: 半导体器件包括衬底，第一栅极，第二栅极和绝缘结构。 基板包括第一翅片和第二翅片。 第一个门被放置在第一个鳍上。 第二个门设置在第二个翅片上。 在第一栅极和第二栅极之间形成间隙，并且间隙朝向衬底变宽。 绝缘结构设置在间隙中。 绝缘结构具有彼此相对的顶表面和底表面。 底面朝向基板。 面向第一门的顶面的边​​缘在顶面向内弯曲。

公开(公告)号：US20160276271A1

公开(公告)日：2016-09-22

申请号：US14658525

申请日：2015-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting CHEN ,  Che-Cheng CHANG ,  Chen-Hsiang LU ,  Yu-Cheng LIU

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522

CPC classification number: H01L21/76804 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76832 ,  H01L23/53295

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a trench. The semiconductor device structure includes a conductive line in the trench. The conductive line has a first end portion and a second end portion. The first end portion faces the substrate. The second end portion faces away from the substrate. A first width of the first end portion is greater than a second width of the second end portion.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括衬底。 半导体器件结构包括在衬底上的电介质层。 电介质层具有沟槽。 半导体器件结构包括沟槽中的导电线。 导线具有第一端部和第二端部。 第一端部面向基板。 第二端部远离基板。 第一端部的第一宽度大于第二端部的第二宽度。