公开(公告)号：US09954105B2

公开(公告)日：2018-04-24

申请号：US15707216

申请日：2017-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yin Lin ,  Teng-Chun Tsai ,  Po-Yu Lin

IPC: H01L27/12 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02631 ,  H01L21/30625 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

公开(公告)号：US10535523B1

公开(公告)日：2020-01-14

申请号：US16117234

申请日：2018-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Lin ,  Chi-Yu Chou ,  Hsien-Ming Lee ,  Huai-Tei Yang ,  Chun-Chieh Wang ,  Yueh-Ching Pai ,  Chi-Jen Yang ,  Tsung-Ta Tang ,  Yi-Ting Wang

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/285

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

公开(公告)号：US20180019338A1

公开(公告)日：2018-01-18

申请号：US15707216

申请日：2017-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yin Lin ,  Teng-Chun Tsai ,  Po-Yu Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/84 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02631 ,  H01L21/30625 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

公开(公告)号：US12170202B2

公开(公告)日：2024-12-17

申请号：US18149129

申请日：2023-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Lin ,  Chi-Yu Chou ,  Hsien-Ming Lee ,  Huai-Tei Yang ,  Chun-Chieh Wang ,  Yueh-Ching Pai ,  Chi-Jen Yang ,  Tsung-Ta Tang ,  Yi-Ting Wang

IPC: H01L23/00 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/49

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

公开(公告)号：US11545363B2

公开(公告)日：2023-01-03

申请号：US17128408

申请日：2020-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Lin ,  Chi-Yu Chou ,  Hsien-Ming Lee ,  Huai-Tei Yang ,  Chun-Chieh Wang ,  Yueh-Ching Pai ,  Chi-Jen Yang ,  Tsung-Ta Tang ,  Yi-Ting Wang

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/285

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

公开(公告)号：US20200350434A1

公开(公告)日：2020-11-05

申请号：US16927376

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yin Lin ,  Teng-Chun Tsai ,  Po-Yu Lin

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

公开(公告)号：US10714615B2

公开(公告)日：2020-07-14

申请号：US16222322

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yin Lin ,  Teng-Chun Tsai ,  Po-Yu Lin

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/66

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

公开(公告)号：US10164102B2

公开(公告)日：2018-12-25

申请号：US15959613

申请日：2018-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yin Lin ,  Teng-Chun Tsai ,  Po-Yu Lin

IPC: H01L21/311 ,  H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L29/66 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

公开(公告)号：US20180240909A1

公开(公告)日：2018-08-23

申请号：US15959613

申请日：2018-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yin Lin ,  Teng-Chun Tsai ,  Po-Yu Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/84 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02631 ,  H01L21/30625 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

公开(公告)号：US09768303B2

公开(公告)日：2017-09-19

申请号：US15226746

申请日：2016-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yin Lin ,  Teng-Chun Tsai ,  Po-Yu Lin

IPC: H01L21/311 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L21/306 ,  H01L21/84

CPC classification number: H01L29/7849 ,  H01L21/02631 ,  H01L21/30625 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.