公开(公告)号：US20240332298A1

公开(公告)日：2024-10-03

申请号：US18738649

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/285 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/4757 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/485 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/02057 ,  H01L21/28525 ,  H01L21/302 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/47573 ,  H01L21/76801 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/485 ,  H01L27/0924 ,  H01L29/7848 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/665

Abstract: A semiconductor device includes a first transistor in a first region of a first conductivity type and a second transistor in a second region of a second conductivity type opposite to the first conductivity type. The first transistor includes a first gate stack, a first epitaxial feature in a source/drain (S/D) region of the first region, and a first metal silicide layer over the first epitaxial feature. The second transistor includes a second gate stack, a second epitaxial feature in an S/D region of the second region, a dopant-containing implant layer over the second epitaxial feature, and a second metal silicide layer over the dopant-containing implant layer. The dopant-containing implant layer includes a metallic dopant. A lowest point of a top surface of the first epitaxial feature is below a lowest point of a top surface of the second epitaxial feature.

公开(公告)号：US11532504B2

公开(公告)日：2022-12-20

申请号：US16985555

申请日：2020-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  Fu-Kai Yang

IPC: H01L29/165 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/033 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78 ,  H01L21/285

Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.

公开(公告)号：US11145554B2

公开(公告)日：2021-10-12

申请号：US16688107

申请日：2019-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  I-Wen Wu ,  Fu-Kai Yang ,  Jia-Heng Wang ,  Mei-Yun Wang

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L21/02 ,  H01L21/324 ,  H01L21/768 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/45 ,  H01L29/165 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065

Abstract: A semiconductor device includes an n-type FET device and a p-type FET device. The n-type FET device includes a first substrate region, a first gate stack, a first gate spacer over sidewalls of the first gate stack, and an n-type epitaxial feature in a source/drain (S/D) region of the n-type FET device. The p-type FET device includes a second substrate region, a second gate stack, a second gate spacer over sidewalls of the second gate stack, and a p-type epitaxial feature in an S/D region of the p-type FET device. A vertical distance between a bottom surface of the first gate spacer and a lowest point of an upper surface of the n-type epitaxial feature is greater than a vertical distance between a bottom surface of the second gate spacer and a lowest point of an upper surface of the p-type epitaxial feature.

公开(公告)号：US20200083119A1

公开(公告)日：2020-03-12

申请号：US16688138

申请日：2019-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  I-Wen Wu ,  Fu-Kai Yang ,  Jia-Heng Wang ,  Mei-Yun Wang

IPC: H01L21/8238 ,  H01L27/06 ,  H01L29/78 ,  H01L29/45 ,  H01L29/167 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L27/092 ,  H01L23/535 ,  H01L21/768 ,  H01L21/324 ,  H01L21/02

Abstract: A method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, and a first source/drain (S/D) feature and a second S/D feature over the substrate. The first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, the first S/D feature is configured for an n-type transistor, and the second S/D feature is configured for a p-type transistor. The method further includes introducing a p-type dopant into both the first and the second S/D features. After the introducing of the p-type dopant, the method further includes performing an etching process to the first and the second S/D features, wherein the etching process etches the first S/D feature faster than it etches the second S/D feature.

公开(公告)号：US11217492B2

公开(公告)日：2022-01-04

申请号：US16688138

申请日：2019-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  I-Wen Wu ,  Fu-Kai Yang ,  Jia-Heng Wang ,  Mei-Yun Wang

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L21/02 ,  H01L21/324 ,  H01L21/768 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/45 ,  H01L29/165 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065

Abstract: A method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, and a first source/drain (S/D) feature and a second S/D feature over the substrate. The first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, the first S/D feature is configured for an n-type transistor, and the second S/D feature is configured for a p-type transistor. The method further includes introducing a p-type dopant into both the first and the second S/D features. After the introducing of the p-type dopant, the method further includes performing an etching process to the first and the second S/D features, wherein the etching process etches the first S/D feature faster than it etches the second S/D feature.

公开(公告)号：US20200083118A1

公开(公告)日：2020-03-12

申请号：US16688107

申请日：2019-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  I-Wen Wu ,  Fu-Kai Yang ,  Jia-Heng Wang ,  Mei-Yun Wang

IPC: H01L21/8238 ,  H01L27/06 ,  H01L29/78 ,  H01L29/45 ,  H01L29/167 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L27/092 ,  H01L23/535 ,  H01L21/768 ,  H01L21/324 ,  H01L21/02

Abstract: A semiconductor device includes an n-type FET device and a p-type FET device. The n-type FET device includes a first substrate region, a first gate stack, a first gate spacer over sidewalls of the first gate stack, and an n-type epitaxial feature in a source/drain (S/D) region of the n-type FET device. The p-type FET device includes a second substrate region, a second gate stack, a second gate spacer over sidewalls of the second gate stack, and a p-type epitaxial feature in an S/D region of the p-type FET device. A vertical distance between a bottom surface of the first gate spacer and a lowest point of an upper surface of the n-type epitaxial feature is greater than a vertical distance between a bottom surface of the second gate spacer and a lowest point of an upper surface of the p-type epitaxial feature.

公开(公告)号：US11037924B2

公开(公告)日：2021-06-15

申请号：US15867058

申请日：2018-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/4757 ,  H01L21/302 ,  H01L21/285 ,  H01L23/485 ,  H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/8238 ,  H01L21/306 ,  H01L29/66 ,  H01L29/417 ,  H01L29/165

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiments, the method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, a first source/drain (S/D) feature comprising silicon adjacent to the first gate structure, a second S/D feature comprising silicon germanium (SiGe) adjacent to the second gate structure; and one or more dielectric layers over sidewalls of the first and second gate structures and over the first and second S/D features. The method further includes etching the one or more dielectric layers to form openings exposing the first and second S/D features, forming a masking layer over the first S/D feature, implanting gallium (Ga) into the second S/D feature while the masking layer is over the first S/D feature, removing the masking layer; and etching the first and second S/D features with an oxygen-atom-containing etchant.

公开(公告)号：US20190157269A1

公开(公告)日：2019-05-23

申请号：US15867058

申请日：2018-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L27/092 ,  H01L23/485 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/4757 ,  H01L21/311 ,  H01L21/302 ,  H01L21/768

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiments, the method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, a first source/drain (S/D) feature comprising silicon adjacent to the first gate structure, a second S/D feature comprising silicon germanium (SiGe) adjacent to the second gate structure; and one or more dielectric layers over sidewalls of the first and second gate structures and over the first and second S/D features. The method further includes etching the one or more dielectric layers to form openings exposing the first and second S/D features, forming a masking layer over the first S/D feature, implanting gallium (Ga) into the second S/D feature while the masking layer is over the first S/D feature, removing the masking layer; and etching the first and second S/D features with an oxygen-atom-containing etchant.

公开(公告)号：US20190067130A1

公开(公告)日：2019-02-28

申请号：US15686698

申请日：2017-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  I-Wen Wu ,  Fu-Kai Yang ,  Jia-Heng Wang ,  Mei-Yun Wang

IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/324 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/45 ,  H01L29/78 ,  H01L23/535 ,  H01L27/092

Abstract: A method includes providing a structure that includes a substrate; first and second gate structures over the substrate; first and second source/drain (S/D) features over the substrate; a first dielectric layer over sidewalls of the first and second gate structures and the first and second S/D features; and a second dielectric layer over the first dielectric layer. The first and second S/D features are adjacent to the first and second gate structures respectively. The first and second S/D features comprise different materials. The method further includes etching the first and second dielectric layers to expose the first and second S/D features; doping a p-type dopant to the first and second S/D features; and performing a selective etching process to the first and second S/D features after the doping of the p-type dopant. The selective etching process recesses the first S/D feature faster than it recesses the second S/D feature.

公开(公告)号：US12068191B2

公开(公告)日：2024-08-20

申请号：US18068041

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming Koh ,  Chen-Ming Lee ,  Fu-Kai Yang

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/283 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/285 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L21/76805 ,  H01L21/0332 ,  H01L21/283 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/66545 ,  H01L21/28518 ,  H01L21/76834 ,  H01L21/823425 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7848

Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.