中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4 records (took 0.012 seconds)

    Memory device
    1.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US09318190B1

    公开(公告)日：2016-04-19

    申请号：US14501623

    申请日：2014-09-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tzu-Kuei Lin ,  Hung-Jen Liao ,  Yen-Huei Chen

    IPC: G11C11/00 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/14

    Abstract: An electronic device is disclosed that includes n memory cells, a replica memory array, and a sensing unit. Each of the n memory cells stores bit data, in which n is a positive integer. The replica memory array includes a first reference memory cell having a high logic state, a second reference memory cell having a low logic state, n−1 first pseudo reference memory cells having the low logic state, and n−1 second pseudo reference memory cells having the high logic state. The first reference memory cell and the n−1 first pseudo reference memory cells generate a first signal, and the second reference memory cell and the n−1 second pseudo reference memory cells generate a second signal. The sensing unit determines a logic state of the bit data of one of the n memory cells according to the first signal and the second signal.

    Abstract translation: 公开了一种包括n个存储单元，复制存储器阵列和感测单元的电子设备。 n个存储单元中的每一个存储位数据，其中n是正整数。 复制存储器阵列包括具有高逻辑状态的第一参考存储单元，具有低逻辑状态的第二参考存储单元，具有低逻辑状态的n-1个第一伪参考存储器单元和n-1个第二伪参考存储器单元 具有高逻辑状态。 第一参考存储单元和n-1个第一伪参考存储单元产生第一信号，第二参考存储单元和第n-1个第二伪参考存储单元产生第二信号。 感测单元根据第一信号和第二信号确定n个存储器单元之一的位数据的逻辑状态。

    Memory device
    3.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US09552873B2

    公开(公告)日：2017-01-24

    申请号：US15016172

    申请日：2016-02-04

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tzu-Kuei Lin ,  Hung-Jen Liao ,  Yen-Huei Chen

    IPC: G11C11/00 ,  G11C11/419 ,  G11C7/14

    CPC classification number: G11C11/419 ,  G11C7/14

    Abstract: A device includes memory cells, reference memory cells, and a sensing unit. The reference memory cells are configured to store first bit data, second bit data, third bit data, and fourth bit data, in which the first bit data and the fourth bit data are configured to be a high logic state, and the second bit data and the third bit data are configured to be a low logic state. The sensing unit is configured to read bit data stored in one of the memory cells according to the first bit data, the second bit data, the third bit data, and the fourth bit data.

    Abstract translation: 一种设备包括存储单元，参考存储单元和感测单元。 参考存储单元被配置为存储第一位数据和第四位数据被配置为高逻辑状态的第一位数据，第二位数据，第三位数据和第四位数据，并且第二位数据 并且第三位数据被配置为低逻辑状态。 感测单元被配置为根据第一位数据，第二位数据，第三位数据和第四位数据读取存储在一个存储器单元中的位数据。

Patent Agency Ranking