公开(公告)号：US20240371951A1

公开(公告)日：2024-11-07

申请号：US18776399

申请日：2024-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chien Liu ,  Yao-Chung Chang ,  Chun Lin Tsai

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.

公开(公告)号：US12132088B2

公开(公告)日：2024-10-29

申请号：US17353051

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chien Liu ,  Yao-Chung Chang ,  Chun Lin Tsai

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/41766 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7783

Abstract: Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.

公开(公告)号：US11450749B2

公开(公告)日：2022-09-20

申请号：US16884292

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Chung Chang ,  Chun Lin Tsai ,  Ru-Yi Su ,  Wei Wang ,  Wei-Chen Yang

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/868

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a buffer layer disposed between an active layer and a substrate. The active layer overlies the substrate. The substrate and the buffer layer include a plurality of pillar structures that extend vertically from a bottom surface of the active layer in a direction away from the active layer. A top electrode overlies an upper surface of the active layer. A bottom electrode underlies the substrate. The bottom electrode includes a conductive body and a plurality of conductive structures that respectively extend continuously from the conductive body, along sidewalls of the pillar structures, to a lower surface of the active layer.

公开(公告)号：US20220037518A1

公开(公告)日：2022-02-03

申请号：US17343153

申请日：2021-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Wang ,  Wei-Chen Yang ,  Yao-Chung Chang ,  Ru-Yi Su ,  Yen-Ku Lin ,  Chuan-Wei Tsou ,  Chun Lin Tsai

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.

公开(公告)号：US20160111501A1

公开(公告)日：2016-04-21

申请号：US14516696

申请日：2014-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chih Chen ,  Jiun-Lei Jerry Yu ,  Yu-Syuan Lin ,  Yao-Chung Chang ,  King-Yuen Wong

IPC: H01L29/205 ,  H01L29/423 ,  H03K17/687 ,  H01L23/31 ,  H01L29/66 ,  H01L29/778 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/205 ,  H01L23/3171 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L2924/0002 ,  H03K17/687 ,  H01L2924/00

Abstract: A group III-V transistor device employing a novel layout for isolating and/or defining the active region is provided. A group III-V heterojunction is arranged over or within a substrate, and an inner drain electrode is arranged over the group III-V heterojunction. A gate has a ring shape and is arranged over the group III-V heterojunction around the inner drain electrode. An outer source electrode has a ring-shaped region arranged over the group III-V heterojunction around the gate. A method for manufacturing the group III-V transistor device is also provided.

Abstract translation: 提供了采用用于隔离和/或限定有源区域的新颖布局的III-V族晶体管器件。 III-V族异质结组置于衬底之上或之内，内部漏电极设置在III-V族异质结上。 栅极具有环形并且布置在围绕内部漏电极的III-V族异质结上。 外源电极具有围绕栅极的III-V族异质结布置的环状区域。 还提供了用于制造III-V族晶体管器件的方法。

公开(公告)号：US09397168B2

公开(公告)日：2016-07-19

申请号：US14516696

申请日：2014-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chih Chen ,  Jiun-Lei Jerry Yu ,  Yu-Syuan Lin ,  Yao-Chung Chang ,  King-Yuen Wong

IPC: H01L29/66 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L23/31 ,  H01L29/778 ,  H03K17/687

CPC classification number: H01L29/205 ,  H01L23/3171 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L2924/0002 ,  H03K17/687 ,  H01L2924/00

Abstract: A group III-V transistor device employing a novel layout for isolating and/or defining the active region is provided. A group III-V heterojunction is arranged over or within a substrate, and an inner drain electrode is arranged over the group III-V heterojunction. A gate has a ring shape and is arranged over the group III-V heterojunction around the inner drain electrode. An outer source electrode has a ring-shaped region arranged over the group III-V heterojunction around the gate. A method for manufacturing the group III-V transistor device is also provided.

Abstract translation: 提供了采用用于隔离和/或限定有源区域的新颖布局的III-V族晶体管器件。 III-V族异质结组置于衬底之上或之内，内部漏电极设置在III-V族异质结上。 栅极具有环形并且布置在围绕内部漏电极的III-V族异质结上。 外源电极具有围绕栅极的III-V族异质结布置的环状区域。 还提供了用于制造III-V族晶体管器件的方法。

公开(公告)号：US20240379836A1

公开(公告)日：2024-11-14

申请号：US18784121

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Wang ,  Wei-Chen Yang ,  Yao-Chung Chang ,  Ru-Yi Su ,  Yen-Ku Lin ,  Chuan-Wei Tsou ,  Chun Lin Tsai

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.

公开(公告)号：US20220336600A1

公开(公告)日：2022-10-20

申请号：US17353051

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chien Liu ,  Yao-Chung Chang ,  Chun Lin Tsai

IPC: H01L29/417 ,  H01L29/778 ,  H01L29/66 ,  H01L29/40

Abstract: Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.

公开(公告)号：US20210376090A1

公开(公告)日：2021-12-02

申请号：US16884292

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Chung Chang ,  Chun Lin Tsai ,  Ru-Yi Su ,  Wei Wang ,  Wei-Chen Yang

IPC: H01L29/417 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a buffer layer disposed between an active layer and a substrate. The active layer overlies the substrate. The substrate and the buffer layer include a plurality of pillar structures that extend vertically from a bottom surface of the active layer in a direction away from the active layer. A top electrode overlies an upper surface of the active layer. A bottom electrode underlies the substrate. The bottom electrode includes a conductive body and a plurality of conductive structures that respectively extend continuously from the conductive body, along sidewalls of the pillar structures, to a lower surface of the active layer.