公开(公告)号：US20220367495A1

公开(公告)日：2022-11-17

申请号：US17815043

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Jou WU ,  Chih-Ming LEE ,  Keng-Ying LIAO ,  Ping-Pang Hsieh ,  Su-Yu YEH ,  Hsin-Hui LIN ,  Yu-Liang WANG

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  G11C8/14

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

公开(公告)号：US20230389309A1

公开(公告)日：2023-11-30

申请号：US18447965

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Jou WU ,  Hsin-Hui Lin ,  Yu-Liang Wang ,  Chih-Ming Lee ,  Keng-Ying Liao ,  Ping-Pang Hsieh ,  Su-Yu Yeh

IPC: H10B41/35 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  G11C8/14 ,  H10B41/10

CPC classification number: H10B41/35 ,  H01L29/788 ,  H10B41/10 ,  H01L29/66825 ,  G11C8/14 ,  H01L29/42324

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.