公开(公告)号：US20240047496A1

公开(公告)日：2024-02-08

申请号：US18488592

申请日：2023-10-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Yu LIN ,  Keng-Ying LIAO ,  Su-Yu YEH ,  Po-Zen CHEN ,  Huai-Jen TUNG ,  Hsien-Li CHEN

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14645 ,  H01L27/14621 ,  H01L27/14689 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/14627

Abstract: An image sensor includes a substrate, a grid, and a color filter. The grid is over the substrate. From a cross-sectional view, the grid includes a first grid and a second grid over the first grid, the first grid has lower portion that has a first sidewall and a second sidewall opposing the first sidewall, the second grid has a third sidewall and a fourth sidewall opposing the third sidewall, and a width between the third sidewall and the fourth sidewall is less than a width between the first sidewall and the second sidewall. The color filter extends through the grid structure.

公开(公告)号：US20210408023A1

公开(公告)日：2021-12-30

申请号：US16916959

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Y.J. WU ,  Chih-Ming LEE ,  Keng-Ying LIAO ,  Ping-Pang Hsieh ,  Su-Yu YEH ,  H.H. LIN ,  Y.L. WANG

IPC: H01L27/11524 ,  H01L27/11519 ,  G11C8/14 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot, performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

公开(公告)号：US20170154891A1

公开(公告)日：2017-06-01

申请号：US15134262

申请日：2016-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Keng-Ying LIAO ,  Po-Zen CHEN ,  Yi-Jie CHEN ,  Yi-Hung CHEN

IPC: H01L27/115 ,  H01L21/311 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/66825

Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.

公开(公告)号：US20230369430A1

公开(公告)日：2023-11-16

申请号：US18358264

申请日：2023-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chu LIN ,  Chi-Chung JEN ,  Chia-Ming PAN ,  Su-Yu YEH ,  Keng-Ying LIAO ,  Chih-Wei SUNG

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788 ,  H10B41/30

CPC classification number: H01L29/42328 ,  H01L29/66825 ,  H01L29/40114 ,  H01L29/7881 ,  H10B41/30

Abstract: A method includes sequentially depositing a floating gate layer, a dielectric structure stack, and a control gate layer over a substrate. A first etching process is performed to pattern the control gate layer, the dielectric structure stack, and a top portion of the floating gate layer to form a control gate, a dielectric structure, and a top portion of a floating gate over a bottom portion of the floating gate layer. A sidewall of the top portion of the floating gate is concave. A first spacer structure is formed on the sidewall of the top portion of the floating gate, a sidewall of the dielectric structure, and a sidewall of the control gate. A second etching process is performed to pattern the bottom portion of the floating gate layer to form a bottom portion of the floating gate after forming the first spacer structure.

公开(公告)号：US20210020669A1

公开(公告)日：2021-01-21

申请号：US16511803

申请日：2019-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Yu LIN ,  Keng-Ying LIAO ,  Huai-Jen TUNG ,  Po-Zen CHEN ,  Su-Yu YEH ,  Chia-Yun CHEN ,  Ta-Cheng WEI

IPC: H01L27/146 ,  H01L21/306 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/768 ,  H01L31/18

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process.

公开(公告)号：US20170170024A1

公开(公告)日：2017-06-15

申请号：US15444039

申请日：2017-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Keng-Ying LIAO ,  Chung-Bin TSENG ,  Po-Zen CHEN ,  Yi-Hung CHEN ,  Yi-Jie CHEN

IPC: H01L21/3065 ,  H01L29/66 ,  H01L21/28 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/31127 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.

公开(公告)号：US20230120006A1

公开(公告)日：2023-04-20

申请号：US18066762

申请日：2022-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Yu LIN ,  Keng-Ying LIAO ,  Su-Yu YEH ,  Po-Zen CHEN ,  Huai-Jen TUNG ,  Hsien-Li CHEN

IPC: H01L27/146

Abstract: A method incudes forming a plurality of photodiodes in a substrate; forming an interconnect structure on a front-side of the substrate; forming a barrier layer on a back-side of the substrate; depositing a metal layer over the barrier layer; forming an adhesion enhancement layer over the metal layer; forming an oxide layer over the adhesion enhancement layer; etching the oxide layer, the adhesion enhancement layer, the metal layer, and the barrier layer to form an oxide grid, an adhesion enhancement grid, a metal grid, and a barrier grid, respectively, wherein the barrier grid and the adhesion enhancement grid have a same chemical element.

公开(公告)号：US20220367495A1

公开(公告)日：2022-11-17

申请号：US17815043

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Jou WU ,  Chih-Ming LEE ,  Keng-Ying LIAO ,  Ping-Pang Hsieh ,  Su-Yu YEH ,  Hsin-Hui LIN ,  Yu-Liang WANG

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  G11C8/14

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

公开(公告)号：US20220216315A1

公开(公告)日：2022-07-07

申请号：US17698748

申请日：2022-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chu LIN ,  Chi-Chung JEN ,  Chia-Ming PAN ,  Su-Yu YEH ,  Keng-Ying LIAO ,  Chih-Wei SUNG

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

Abstract: A method includes depositing a gate dielectric film over a substrate. A floating gate layer and a control gate layer are deposited over the gate dielectric film. The control gate layer is patterned to form a control gate over the floating gate layer. A top portion of the floating gate layer is patterned. A spacer structure is formed on a sidewall of the control gate and over a remaining portion of the floating gate layer. The remaining portion of the floating gate layer is patterned to form a bottom portion of a floating gate. A ratio of the bottom width of the bottom portion to the middle width of the bottom portion is in a range between about 103% and about 108%. The gate dielectric film is patterned form a gate dielectric layer.

公开(公告)号：US20210225918A1

公开(公告)日：2021-07-22

申请号：US16746720

申请日：2020-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Yu LIN ,  Keng-Ying LIAO ,  Su-Yu YEH ,  Po-Zen CHEN ,  Huai-Jen TUNG ,  Hsien-Li CHEN

IPC: H01L27/146

Abstract: An image sensor structure includes a semiconductor device, a plurality of image sensing elements formed in the semiconductor substrate, an interconnect structure formed on the semiconductor substrate, and a composite grid structure over the semiconductor substrate. The composite grid structure includes a tungsten grid, an oxide grid over the tungsten grid, and an adhesion enhancement grid spacing the tungsten grid from the oxide grid.