公开(公告)号：US20240047496A1

公开(公告)日：2024-02-08

申请号：US18488592

申请日：2023-10-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Yu LIN ,  Keng-Ying LIAO ,  Su-Yu YEH ,  Po-Zen CHEN ,  Huai-Jen TUNG ,  Hsien-Li CHEN

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14645 ,  H01L27/14621 ,  H01L27/14689 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/14627

Abstract: An image sensor includes a substrate, a grid, and a color filter. The grid is over the substrate. From a cross-sectional view, the grid includes a first grid and a second grid over the first grid, the first grid has lower portion that has a first sidewall and a second sidewall opposing the first sidewall, the second grid has a third sidewall and a fourth sidewall opposing the third sidewall, and a width between the third sidewall and the fourth sidewall is less than a width between the first sidewall and the second sidewall. The color filter extends through the grid structure.

公开(公告)号：US20210408023A1

公开(公告)日：2021-12-30

申请号：US16916959

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Y.J. WU ,  Chih-Ming LEE ,  Keng-Ying LIAO ,  Ping-Pang Hsieh ,  Su-Yu YEH ,  H.H. LIN ,  Y.L. WANG

IPC: H01L27/11524 ,  H01L27/11519 ,  G11C8/14 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot, performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

公开(公告)号：US20190157124A1

公开(公告)日：2019-05-23

申请号：US16127919

申请日：2018-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chieh HSIEH ,  Su-Yu YEH ,  Ko-Bin KAO ,  Chia-Hung CHUNG ,  Li-Jen WU ,  Chun-Yu CHEN ,  Hung-Ming CHEN ,  Yong-Ting WU

IPC: H01L21/67 ,  H01L21/673 ,  G01N33/00

Abstract: A method for monitoring gas in a wafer processing system is provided. The method includes producing an exhaust flow in an exhausting conduit from a processing chamber. The method further includes placing a gas sensor in fluid communication with a detection point located in the exhausting conduit via a sampling tube that passes through a through hole formed on the exhausting conduit. The detection point is located away from the through hole. The method also includes detecting a gas condition at the detection point with the gas sensor. In addition, the method also includes analyzing the gas condition detected by the gas sensor to determine if the gas condition in the exhausting conduit is in a range of values.

公开(公告)号：US20220359598A1

公开(公告)日：2022-11-10

申请号：US17871890

申请日：2022-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Yu LIN ,  Keng-Ying LIAO ,  Su-Yu YEH ,  Po-Zen CHEN ,  Huai-Jen TUNG ,  Hsien-Li CHEN

IPC: H01L27/146

Abstract: An image sensor structure includes a semiconductor device, a plurality of image sensing elements formed in the semiconductor substrate, an interconnect structure formed on the semiconductor substrate, and a composite grid structure over the semiconductor substrate. The composite grid structure includes a tungsten grid, an oxide grid over the tungsten grid, and an adhesion enhancement grid spacing the tungsten grid from the oxide grid.

公开(公告)号：US20200043762A1

公开(公告)日：2020-02-06

申请号：US16233701

申请日：2018-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Kai CHEN ,  Chia-Hung CHUNG ,  Ko-Bin KAO ,  Shi-Ming WANG ,  Su-Yu YEH ,  Li-Jen WU ,  Oliver YU ,  Wen-Shiung CHEN

IPC: H01L21/67 ,  G03F7/16

Abstract: The present disclosure describes a container for placing an object therein. The container includes a container body and a lid over the container body, a collision-preventing portion attached to one or more of the container body and the lid and configured to buffer an impact force, a pairing recognition mechanism configured to detect an object placed in the container body, and a liquid-detecting sensor configured to detect a leakage from the object.

公开(公告)号：US20230369430A1

公开(公告)日：2023-11-16

申请号：US18358264

申请日：2023-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chu LIN ,  Chi-Chung JEN ,  Chia-Ming PAN ,  Su-Yu YEH ,  Keng-Ying LIAO ,  Chih-Wei SUNG

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788 ,  H10B41/30

CPC classification number: H01L29/42328 ,  H01L29/66825 ,  H01L29/40114 ,  H01L29/7881 ,  H10B41/30

Abstract: A method includes sequentially depositing a floating gate layer, a dielectric structure stack, and a control gate layer over a substrate. A first etching process is performed to pattern the control gate layer, the dielectric structure stack, and a top portion of the floating gate layer to form a control gate, a dielectric structure, and a top portion of a floating gate over a bottom portion of the floating gate layer. A sidewall of the top portion of the floating gate is concave. A first spacer structure is formed on the sidewall of the top portion of the floating gate, a sidewall of the dielectric structure, and a sidewall of the control gate. A second etching process is performed to pattern the bottom portion of the floating gate layer to form a bottom portion of the floating gate after forming the first spacer structure.

公开(公告)号：US20210020669A1

公开(公告)日：2021-01-21

申请号：US16511803

申请日：2019-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Yu LIN ,  Keng-Ying LIAO ,  Huai-Jen TUNG ,  Po-Zen CHEN ,  Su-Yu YEH ,  Chia-Yun CHEN ,  Ta-Cheng WEI

IPC: H01L27/146 ,  H01L21/306 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/768 ,  H01L31/18

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process.

公开(公告)号：US20190148333A1

公开(公告)日：2019-05-16

申请号：US15870569

申请日：2018-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Chih CHEN ,  Tsung-Yi YANG ,  Chung-I HUNG ,  Mu-Han CHENG ,  Tzu-Shin CHEN ,  Su-Yu YEH

IPC: H01L23/00 ,  H01L21/66

Abstract: A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected.

公开(公告)号：US20230120006A1

公开(公告)日：2023-04-20

申请号：US18066762

申请日：2022-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Yu LIN ,  Keng-Ying LIAO ,  Su-Yu YEH ,  Po-Zen CHEN ,  Huai-Jen TUNG ,  Hsien-Li CHEN

IPC: H01L27/146

Abstract: A method incudes forming a plurality of photodiodes in a substrate; forming an interconnect structure on a front-side of the substrate; forming a barrier layer on a back-side of the substrate; depositing a metal layer over the barrier layer; forming an adhesion enhancement layer over the metal layer; forming an oxide layer over the adhesion enhancement layer; etching the oxide layer, the adhesion enhancement layer, the metal layer, and the barrier layer to form an oxide grid, an adhesion enhancement grid, a metal grid, and a barrier grid, respectively, wherein the barrier grid and the adhesion enhancement grid have a same chemical element.

公开(公告)号：US20220367495A1

公开(公告)日：2022-11-17

申请号：US17815043

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Jou WU ,  Chih-Ming LEE ,  Keng-Ying LIAO ,  Ping-Pang Hsieh ,  Su-Yu YEH ,  Hsin-Hui LIN ,  Yu-Liang WANG

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  G11C8/14

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.