公开(公告)号：US11804529B2

公开(公告)日：2023-10-31

申请号：US17698748

申请日：2022-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chu Lin ,  Chi-Chung Jen ,  Chia-Ming Pan ,  Su-Yu Yeh ,  Keng-Ying Liao ,  Chih-Wei Sung

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788 ,  H10B41/30

CPC classification number: H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881 ,  H10B41/30

Abstract: A method includes depositing a gate dielectric film over a substrate. A floating gate layer and a control gate layer are deposited over the gate dielectric film. The control gate layer is patterned to form a control gate over the floating gate layer. A top portion of the floating gate layer is patterned. A spacer structure is formed on a sidewall of the control gate and over a remaining portion of the floating gate layer. The remaining portion of the floating gate layer is patterned to form a bottom portion of a floating gate. A ratio of the bottom width of the bottom portion to the middle width of the bottom portion is in a range between about 103% and about 108%. The gate dielectric film is patterned form a gate dielectric layer.

公开(公告)号：US11527543B2

公开(公告)日：2022-12-13

申请号：US16916959

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Jou Wu ,  Chih-Ming Lee ,  Keng-Ying Liao ,  Ping-Pang Hsieh ,  Su-Yu Yeh ,  Hsin-Hui Lin ,  Yu-Liang Wang

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  G11C8/14

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot, performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

公开(公告)号：US20250014946A1

公开(公告)日：2025-01-09

申请号：US18348967

申请日：2023-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fan Hsuan Chien ,  Su-Yu Yeh ,  Teng-Ta Hung ,  Chun-Jen Chen ,  Pei Yen Cheng ,  Shih-Chi Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: A method includes etching a gate stack to form a trench extending through the gate stack, the gate stack including a metal gate electrode and a gate dielectric, wherein forming the trench removes a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion; extending the trench through an isolation region under the gate stack and into a semiconductor substrate under the isolation region; conformally depositing a first dielectric material on surfaces in the trench; and depositing a second dielectric material on the first dielectric material to fill the trench, wherein the first dielectric material is a more flexible material than the second dielectric material.

公开(公告)号：US20230389309A1

公开(公告)日：2023-11-30

申请号：US18447965

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Jou WU ,  Hsin-Hui Lin ,  Yu-Liang Wang ,  Chih-Ming Lee ,  Keng-Ying Liao ,  Ping-Pang Hsieh ,  Su-Yu Yeh

IPC: H10B41/35 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  G11C8/14 ,  H10B41/10

CPC classification number: H10B41/35 ,  H01L29/788 ,  H10B41/10 ,  H01L29/66825 ,  G11C8/14 ,  H01L29/42324

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

公开(公告)号：US10943802B2

公开(公告)日：2021-03-09

申请号：US16233701

申请日：2018-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Kai Chen ,  Chia-Hung Chung ,  Ko-Bin Kao ,  Shi-Ming Wang ,  Su-Yu Yeh ,  Li-Jen Wu ,  Oliver Yu ,  Wen-Shiung Chen

IPC: H01L21/67 ,  G03F7/16

Abstract: The present disclosure describes a container for placing an object therein. The container includes a container body and a lid over the container body, a collision-preventing portion attached to one or more of the container body and the lid and configured to buffer an impact force, a pairing recognition mechanism configured to detect an object placed in the container body, and a liquid-detecting sensor configured to detect a leakage from the object.

公开(公告)号：US12094997B2

公开(公告)日：2024-09-17

申请号：US17814726

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih Wei Sung ,  Chung-Bin Tseng ,  Keng-Ying Liao ,  Yen-Jou Wu ,  Po-Zen Chen ,  Su-Yu Yeh ,  Ching-Chung Su

IPC: H01L31/18 ,  H01L23/544 ,  H01L27/146

CPC classification number: H01L31/1876 ,  H01L23/544 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14683 ,  H01L27/14687 ,  H01L31/186 ,  H01L31/1888 ,  H01L2223/54426

Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

公开(公告)号：US11282931B2

公开(公告)日：2022-03-22

申请号：US16879559

申请日：2020-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chu Lin ,  Chi-Chung Jen ,  Chia-Ming Pan ,  Su-Yu Yeh ,  Keng-Ying Liao ,  Chih-Wei Sung

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

Abstract: A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer.

公开(公告)号：US11061333B2

公开(公告)日：2021-07-13

申请号：US15905739

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Kai Chen ,  Chia-Hung Chung ,  Ko-Bin Kao ,  Su-Yu Yeh ,  Li-Jen Wu ,  Zhi-You Ke ,  Ming-Hung Lin

IPC: G03F7/20 ,  G03F7/40 ,  H01L21/027 ,  H01L21/66 ,  G03F7/039 ,  G03F7/004 ,  G03F7/32 ,  G03F7/16 ,  G03F7/30 ,  H01L29/66 ,  H01L21/67 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device and a semiconductor processing system are provided. The method includes the following steps. A photoresist layer is formed on a substrate in a lithography tool. The photoresist layer is exposed in the lithography tool to form an exposed photoresist layer. The exposed photoresist layer is developed to form a patterned photoresist layer in the lithography tool by using a developer. An ammonia gas by-product of the developer is removed from the lithography tool.

公开(公告)号：US11004709B2

公开(公告)日：2021-05-11

申请号：US16127919

申请日：2018-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chieh Hsieh ,  Su-Yu Yeh ,  Ko-Bin Kao ,  Chia-Hung Chung ,  Li-Jen Wu ,  Chun-Yu Chen ,  Hung-Ming Chen ,  Yong-Ting Wu

IPC: H01L21/67 ,  G01N33/00 ,  H01L21/673 ,  B05C15/00

Abstract: A method for monitoring gas in a wafer processing system is provided. The method includes producing an exhaust flow in an exhausting conduit from a processing chamber. The method further includes placing a gas sensor in fluid communication with a detection point located in the exhausting conduit via a sampling tube that passes through a through hole formed on the exhausting conduit. The detection point is located away from the through hole. The method also includes detecting a gas condition at the detection point with the gas sensor. In addition, the method also includes analyzing the gas condition detected by the gas sensor to determine if the gas condition in the exhausting conduit is in a range of values.

公开(公告)号：US10050159B2

公开(公告)日：2018-08-14

申请号：US15375253

申请日：2016-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Chih Chen ,  Su-Yu Yeh ,  Tzu-Shin Chen ,  Mu-Han Cheng ,  Chun-Hai Huang

IPC: H01L31/0232 ,  G02B3/00 ,  G02B5/20 ,  H01L27/146 ,  H01L31/0352

CPC classification number: H01L31/02327 ,  G02B3/0068 ,  G02B5/201 ,  H01L27/14643

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a dielectric layer is provided. Then, trenches are formed in the dielectric layer. Thereafter, the trenches are filled with spacer material to form a spacer structure in the dielectric layer for defining pixel regions. Then, lens structures are formed on the pixel regions. Each of the lens structures includes a first curved lens layer, a second curved lens layer and a curved color filter layer. The curved color filter layer is disposed on the second curved lens layer or between the first curved lens layer and the second curved lens layer.