公开(公告)号：US20220406662A1

公开(公告)日：2022-12-22

申请号：US17815180

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Wen-Tuo HUANG ,  Yong-Shiuan TSAIR

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28

Abstract: The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.

公开(公告)号：US20210057406A1

公开(公告)日：2021-02-25

申请号：US16549077

申请日：2019-08-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Wen-Tuo HUANG ,  Yong-Shiuan TSAIR

IPC: H01L27/06 ,  H01L21/8234

Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate haying spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

公开(公告)号：US20190229123A1

公开(公告)日：2019-07-25

申请号：US16370736

申请日：2019-03-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsun-Kai TSAO ,  Hung-Ling SHIH ,  Po-Wei LIU ,  Shun-Shing YANG ,  Wen-Tuo HUANG ,  Yong-Shiuan TSAIR ,  S.K. YANG

IPC: H01L27/11529 ,  H01L27/11521 ,  H01L21/3105 ,  H01L21/28 ,  H01L29/423

Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

公开(公告)号：US20220102428A1

公开(公告)日：2022-03-31

申请号：US17032155

申请日：2020-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chieh-Fei CHIU ,  Wen-Ting CHU ,  Yong-Shiuan TSAIR ,  Yu-Wen LIAO ,  Chih-Yang CHANG ,  Chin-Chieh YANG

IPC: H01L27/24 ,  H01L27/1159 ,  H01L27/11592 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L45/00

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

公开(公告)号：US20180019251A1

公开(公告)日：2018-01-18

申请号：US15209370

申请日：2016-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsun-Kai TSAO ,  Hung-Ling SHIH ,  Po-Wei LIU ,  Shun-Shing YANG ,  Wen-Tuo HUANG ,  Yong-Shiuan TSAIR ,  S.K. Yang

IPC: H01L21/28 ,  H01L21/3105

CPC classification number: H01L27/11529 ,  H01L21/28273 ,  H01L21/31056 ,  H01L27/11521 ,  H01L29/42328

Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

公开(公告)号：US20250159904A1

公开(公告)日：2025-05-15

申请号：US19021415

申请日：2025-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chieh-Fei CHIU ,  Wen-Ting CHU ,  Yong-Shiuan TSAIR ,  Yu-Wen LIAO ,  Chih-Yang CHANG ,  Chin-Chieh YANG

IPC: H10B63/00 ,  H10B51/30 ,  H10B51/40 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

Abstract: An integrated circuit includes a metal/dielectric layer, a second dielectric layer, a bottom electrode, a resistance switch element, and a top electrode. The metal/dielectric layer has a first dielectric layer and a conductive feature in the first dielectric layer. The second dielectric layer is over the metal/dielectric layer. The bottom electrode is over and in contact with the conductive feature and surrounded by the second dielectric layer. The second dielectric layer has a tapered sidewall, a lower portion of the tapered sidewall of the second dielectric layer is covered by the bottom electrode, and an upper portion of the tapered sidewall of the second dielectric layer is free from coverage by the bottom electrode. The resistance switch element is over the bottom electrode. The top electrode is over the resistance switch element.

公开(公告)号：US20220223651A1

公开(公告)日：2022-07-14

申请号：US17709845

申请日：2022-03-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chieh-Fei CHIU ,  Yong-Shiuan TSAIR ,  Wen-Ting CHU ,  Yu-Wen LIAO ,  Chin-Yu MEI ,  Po-Hao TSENG

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

公开(公告)号：US20180197873A1

公开(公告)日：2018-07-12

申请号：US15914485

申请日：2018-03-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsun-Kai TSAO ,  Hung-Ling SHIH ,  Po-Wei LIU ,  Shun-Shing YANG ,  Wen-Tuo HUANG ,  Yong-Shiuan TSAIR ,  S.K. Yang

IPC: H01L27/11529 ,  H01L21/3105 ,  H01L21/28

CPC classification number: H01L27/11529 ,  H01L21/28273 ,  H01L21/31056 ,  H01L27/11521 ,  H01L29/42328

Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

公开(公告)号：US20230380190A1

公开(公告)日：2023-11-23

申请号：US18361483

申请日：2023-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chieh-Fei CHIU ,  Wen-Ting CHU ,  Yong-Shiuan TSAIR ,  Yu-Wen LIAO ,  Chih-Yang CHANG ,  Chin-Chieh YANG

IPC: H10B63/00 ,  H10B51/30 ,  H10B51/40 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/30 ,  H10B51/30 ,  H10B51/40 ,  H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/068 ,  H10N70/231 ,  H10N70/253 ,  H10N70/841

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

公开(公告)号：US20210013220A1

公开(公告)日：2021-01-14

申请号：US16506823

申请日：2019-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Wen-Tuo HUANG ,  Yong-Shiuan TSAIR

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/788 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first gate stack. An isolation feature is formed in the semiconductor substrate, and a cell region and a peripheral region adjacent to the cell region are defined in the semiconductor substrate. The first gate stack is disposed on the peripheral region of the semiconductor substrate. The first gate stack includes a first dielectric layer and a gate electrode layer disposed on the first dielectric layer and covering a top surface of the first dielectric layer. The first dielectric layer is disposed on the semiconductor substrate and has a concave profile.